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Electrical Engineering 243

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Submitted By oladotun
Words 648
Pages 3
May 8, 2012

[JOSEPH | OLADOTUN |ANISE]

EEGR243: Computer Architecture
Clarence M. Mitchell, Jr. School of Engineering

Morgan State University
Instructor: Dr. Walker

Project #2
Date Due: March 07, 2011

Team member Oladotun Opasina Richard Joseph Anise Udiani.

EEGR243 Project#2 1

May 8, 2012

[JOSEPH | OLADOTUN |ANISE]

Table of Contents Introduction …………………................................................................................ Requirements Schematics ...................................................................................................................... ................................................................................................................................... ..............................................................................................

Discussion/Analysis/Conclusion

EEGR243 Project#2 2

May 8, 2012

[JOSEPH | OLADOTUN |ANISE]

Introduction: Vhdl is also known as Very High level Speed Integrated Circuit hardware description language it is used for electronic design automation to depict digital and mixed signal systems .The US Department of Defense first developed this to document the behavior of the ASCIS that companies that supplied them with components were including in there equipment. The reason this was ideal was that it provided a platform for engineers in the department of Defense and other entities to figure how exactly certain components work. This project focuses on the ability of Vhdl to simulate the function of components in a schematic while assembled in any particular manner. The project asked us to simulate the operation and schematics of the defined operations: Load Half word Unsigned (LHU): loads the least significant bits of the destination register with contents of the half word that is the memory location specified by the effective address because the machine treats the loads half word as an unsigned value it fills the two most significant bytes of the destination register with zeros. If the effective address is not even the machine signals an address error exception. The LHU is an I-type format Format: lhu rt,offset(rs) 31-26(Opcode) 100101 25-21 rs 20-16 rt 15-0 Offset

EEGR243 Project#2 3

May 8, 2012

[JOSEPH | OLADOTUN |ANISE]

Store byte: The Sb stores from the register rt 1 byte to a memory located at the offset added to the base address of rs. Operations: In the processor, The 16-bit offset is sign-extended and added to the contents of rs to form an address which loaded in the data memory and The least-significant byte of register rt is sign extended and stored at the effective address which is the write port of the data memory.

Format: sb rt,offset(base) 31-26(Opcode) 101000 25-21 rs 20-16 rt 15-0 Offset

Set less than immediate unassigned (SltiU) : compares two assigned 32 bit values of the contents of rs and the offset then stores either a one or zero in the register rt. Operations: The 16-bit immediate is sign-extended and subtracted from the contents of register rs. Considering both quantities as unsigned integers, if rs is less than the sign-extended immediate, the result is set to one; otherwise the result is set to zero. Format: sltiu rt, rs, immediate. It is an I-type format 31-26(Opcode) 001011 25-21 rs 20-16 rt 15-0 Offset

EEGR243 Project#2 4

May 8, 2012

[JOSEPH | OLADOTUN |ANISE]

Branch on equal: branches to the specified label/offset when contents of rt equals to the contents of rs. Operations: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended. The contents of rs and the contents of rt are compared. If the two registers are equal, then the program branches to the target address, with a delay of one instruction. Format: beq rs,rt,offset. It is an I-type format

31-26(Opcode) 000100

25-21 rs

20-16 rt

15-0 Offset

EEGR243 Project#2 5

May 8, 2012

[JOSEPH | OLADOTUN |ANISE]

MIPS CONSOLE CODE:

EEGR243 Project#2 6

May 8, 2012

[JOSEPH | OLADOTUN |ANISE]

Schematic for Controller implementing LHU,SB,SLTIU,SB

32

3

Adder 0_y

OFFSET

3 adder 1_y

+
Offset Sign Extend 15:0

32

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