...536 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 4, APRIL 1999 Comparative Analysis of Master–Slave Latches and Flip-Flops for High-Performance and Low-Power Systems Vladimir Stojanovic and Vojin G. Oklobdzija, Fellow, IEEE Abstract—In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master–slave latch structures. A new simulation and optimization approach is presented, targeting both highperformance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master–slave latches and flipflops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications. Fig. 1. The pseudorandom sequence. I. INTRODUCTION I NTERPRETATION of published results comparing various latches and flip-flops has been very difficult because of the use of different simulation methods for their generation and presentation. In this paper, we establish a set of rules with the goal of making the comparisons fair and realistic. Simulation of the latches and flip-flops obtained by using different design styles makes this analysis more difficult in trying to achieve consistent and...
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... FLIP-FLOP & ITS APPLICATIONS This project is about the flip-flop and its applications in digital electronics. A flip-flop is a synchronous version of the latch. The first electronic flip-flop was invented in 1918 by William Eccles and F.W. Jordan. It was initially called the Eccles–Jordan trigger circuit and consisted of two active elements (vacuum tubes).Such circuits and their transistorized versions were common in computers even after the introduction of integrated circuits, though flip-flops made from logic gates are also common now .Today, the term flip-flop has come to mostly denote non-transparent (clocked or edge triggered) devices, while the simpler transparent ones are often referred to as latches. The word latch is mainly used for storage elements, while clocked devices are described as flip-flops. There are a number of types of Flip-flops such as: - Set-Reset Flip-flops, also known as SR Flip-flops - Toggle Flip-Flops - JK Flip Flops - Master–slave pulse-triggered D flip-flop - D Flip Flops - Gated latches and conditional transparency Flip-flops are essentially 1-bit storage devices .i.e. outputs can be set to store either 0 or 1 depending on the inputs. A flip-flop in combination with a Schmitt trigger can be used for the implementation of an arbiter in asynchronous circuits. Flip-flop integrated circuits (ICs) also exist that provide one or more flip-flops. We can use any one of the flip-flop type to build any of the...
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...To move the generator back and forth between these two states, we use a T-type flip-flop that switches whenever there is a 1 on its data input. If it is set to 0, the generator enters the hold period with all latches temporarily disabled regardless of the control register content. This is accomplished by placing AND gates on the control register outputs to allow freezing of all phase shifter inputs. This property can be crucial in SoC designs where only a single scan chain crosses a given core, and its abnormal toggling may cause locally unacceptable heat dissipation that can only be reduced due to temporary hold periods. If the T flip-flop is set to 1 (the toggle period), then the latches enabled through the control register can pass test data moving from the PRPG to the scan chains. Two additional parameters kept in 4-bit Hold and Toggle registers determine how long the entire generator remains either in the hold mode or in the toggle mode, respectively. To terminate either mode, a 1 must occur on the T flip-flop input. This weighted pseudorandom signal is produced in a manner...
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...Flip-Flops Basic concepts Flip-Flops A flip-flop is a bi-stable device: a circuit having 2 stable conditions (0 or 1) 3 classes of flip-flops latches: outputs respond immediately while enabled (no timing control) pulse-triggered flip-flops: outputs response to the triggering pulse edge-triggered flip-flops: outputs responses to the control input edge A. Yaicharoen 2 1/51 Conventions The circuit is set means output = 1 The circuit is reset means output = 0 Flip-flops have two output Q and Q′ or (Q and Q) Due to time related characteristic of the flipflop, Q and Q′ (or Q) are usually represented as followed: Qt or Q: present state Qt+1 or Q+: next state A. Yaicharoen 3 1/51 4 Types of Flip-Flops SR flip-flop S 0 0 1 1 R 0 1 0 1 Qt+1 Qt 0 1 Q’t+1 Q’t 1 0 JK flip-flop J 0 0 1 1 K 0 1 0 1 Qt+1 Qt 0 1 Q’t Q’t+1 Q’t 1 0 Qt Prohibited D flip-flop D 0 1 1/51 T flip-flop Q’t+1 1 0 A. Yaicharoen Qt+1 0 1 T 0 1 Qt+1 Qt Q’t Q’t+1 Q’t Qt 4 SR Latch An SR (or set-reset) latch consists of S (set) input: set the circuit R (reset) input: reset the circuit Q and Q’ output: output of the SR latch in normal and complement form S 0 0 1 1 R 0 1 0 1 Qt+1 Qt 0 1 Q’t+1 Q’t 1 0 Prohibited Application example: a switch debouncer 1/51 A. Yaicharoen 5 SR latch 1/51 A. Yaicharoen 6 An application of the SR latch (a) Effects of contact bounce. (b) A switch debouncer...
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...2013-2014 INSTRUCTOR CLASS HOURS Mr. Michel Owayjan MWF Room: 3:00 pm - 3:50 pm 404, Block B OFFICE HOURS M-W-F 2:00 pm - 3:00 pm T-TH 12:00 am - 1:00 pm Otherwise by appointment Room: 805, Block A COURSE OBJECTIVES This is a sophomore-level course which addresses the fundamentals of digital systems needed to develop the ability of the student in understanding the concepts related to this area of engineering. The objective is to train the students on the various tools used to solve problems related to the design of digital systems. These include: i) binary number system; ii) conversion between number systems; iii) Boolean algebra; iv) logic gates; v) Karnaugh maps; vi) combinational and sequential logic; vii) SSI and MSI design; viii) flip-flops; ix) counters; x) registers; xi) memories; and, xii) state machines. The problem solving and experimental skills of the student in the above areas are enhanced by a co-requisite Laboratory Course held on a weekly basis. COURSE PREREQUISITES CSI 201: Introduction to Computing PREREQUISITES BY TOPICS The student should have the general background in computers and algebra. COURSE CREDITS 3 Credit Hours INSTRUCTION TECHNIQUE Lectures will be used predominantly. These will be supported by problem sets and design projects, which include virtual instrumentation projects using LabVIEWTM. REQUIRED TEXT Marcovitz A.B. Introduction to Logic Design, Third Edition. McGraw Hill, 2010. REFERENCES Marcovitz A. B. Introduction to Logic Design...
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...Asynchronous Counters Theory: 1. What makes a counter asynchronous? The counter is asynchronous because its clock is only applied to a single flip-flop. 2. What is the modulus or count range of the following counter? 16 cycles will count from 0-15 Planning: 3. What is the purpose of the ELVISmx Dig In instrument? display the output of the counter Test Procedure: 4. Record the observed values from Lab 5 Table 5-1. Record the state number, the value of QDQCQBQA, the hexadecimal and decimal values. StateNumber | DataLine 7 | DataLine 6 | DataLine 5 | DataLine 4 | Hexadecimal | Decimal | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 2 | 0 | 0 | 1 | 0 | 2 | 2 | 3 | 0 | 0 | 1 | 1 | 3 | 3 | 4 | 0 | 1 | 0 | 0 | 4 | 4 | 5 | 0 | 1 | 0 | 1 | 5 | 5 | 6 | 0 | 1 | 1 | 0 | 6 | 6 | 7 | 0 | 1 | 1 | 1 | 7 | 7 | 8 | 1 | 0 | 0 | 0 | 8 | 8 | 9 | 1 | 0 | 0 | 1 | 9 | 9 | 10 | 1 | 0 | 1 | 0 | A | 10 | 11 | 1 | 0 | 1 | 1 | B | 11 | 12 | 1 | 1 | 0 | 0 | C | 12 | 13 | 1 | 1 | 0 | 1 | D | 13 | 14 | 1 | 1 | 1 | 0 | E | 14 | 15 | 1 | 1 | 1 | 1 | F | 15 | | | | | | | | | | | | | | | ------------------------------------------------- Part 2- Implement Synchronous Counters Theory: 5. What makes a counter synchronous? Because its clock is applied to each of the flip-flops. 6. What is the purpose of the ~U/D control signal for the 74191 Synchronous Counter? when low, counts up, when high, counts down ...
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...INTERVIEW /VIVA QUES VLSI DESIGN AND TECHNOLOGY DOWNLOADED FROM: www.freewebs.com\sbalpande\microprocessor c@ S. Balpande. faculty in ET dept ,RCET,Bhilai. DOWNLOADED FROM: www.freewebs.com\sbalpande\microprocessor CMOS interview questions. 1/ What is latch up? Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously flow through it once it is accidentally triggered or turned on. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS) 2)Why is NAND gate preferred over NOR gate for fabrication? NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three times that of holes compared to NOR and thus the NAND is a faster gate. Additionally, the gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more symmetric in case of NAND ( the delay profile), but for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher resistance p mos's are in series connection which again increases the resistance). 3)What is Noise Margin? Explain the procedure to determine Noise Margin The minimum amount of noise that can be allowed on the input stage...
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...TTL Cookbook BY Don Lancaster A Division of M t i c e Hall ComputerPublishing 11 711 Nonh College, Cmel, Indiana 46032 USA " 1974 by SAMS A Division of Prentice Hall Computer Publishing. All rights reserved. No parts of this book shall be reproduced, stored in a retrieval system, or transmitted by any means. electronic, mechanical, photocopying, recording, or otherwise, without written permission from the publisher. No patent liability is assumed with respect to the use of the information contained herein. While every precaution has been taken in the preparation of this book, the publisher assumes no responsibility for errors or omissions. Neither is any liability assumed for damages resulting from the use of the information contained herein. International Standard Book Number: 0-672-21035-5 Library of Congress Catalog Card Number: 73-90295 Interpretation of the printing code: the rightmost double-digit number of the first column is the year of the book's printing; the rightmost double-digit number of the second column, the number of the book's printing. For example, a printing code of 92-23 shows that the twenty-third printing of the book occurred in 1992. Printed in the United States of America. Preface I don't like to revise books. Correct, yes. Revise, no. So I won't. A book becomes history the instant it appears in print. To tamper with history messes with what others and I were thinking at the time and distorts the way things...
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...========================================================================= Final Results RTL Top Level Output File Name : shift_register.ngr Top Level Output File Name : shift_register Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 8 Cell Usage : # BELS : 4 # INV : 1 # LUT3 : 3 # FlipFlops/Latches : 3 # FDC : 3 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 7 # IBUF : 4 # OBUF : 3 ========================================================================= Device utilization summary: --------------------------- Selected Device : 2s15cs144-6 Number of Slices: 2 out of 192 1% Number of Slice Flip Flops: 3 out of 384 0% Number of 4 input LUTs: 4 out of 384 1% Number of IOs: 8 Number of bonded IOBs: 8 out of 86 9% Number of GCLKs: 1 out of 4 25% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- =========================================================================...
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...Random access memory • Sequential circuits all depend upon the presence of memory. – A flip-flop can store one bit of information. – A register can store a single “word,” typically 32-64 bits. • Random access memory, or RAM, allows us to store even larger amounts of data. Today we’ll see: – The basic interface to memory. – How you can implement static RAM chips hierarchically. This is the last piece we need to put together a computer! • Random Access Memory 1 Introduction to RAM • Random-access memory, or RAM, provides large quantities of temporary • storage in a computer system. Remember the basic capabilities of a memory: – It should be able to store a value. – You should be able to read the value that was saved. – You should be able to change the stored value. A RAM is similar, except that it can store many values. – An address will specify which memory value we’re interested in. – Each value can be a multiple-bit word (e.g., 32 bits). We’ll refine the memory properties as follows: A RAM should be able to: - Store many words, one per address - Read the word that was saved at a particular address - Change the word that’s saved at a particular address • • Random Access Memory 2 Picture of memory • You can think of computer memory as being one big array of data. – The address serves as an array index. – Each address refers to one word of data. You can read or modify the data at any given memory address, just like you can read...
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...SCIENTIFIC PUBLICATIONS OF THE STATE UNIVERSITY OF NOVI PAZAR S ER . A: A PPL . M ATH . I NFORM . AND M ECH . vol. 1, 1 (2009), 11-20 Vernier’s Delay Line Time–to–Digital Converter G. S. Jovanovi´ , M. K. Stojˇ ev c c Abstract: This paper describes the architecture and performance of a high-resolution time–to– digital converter (TDC) based on a Vernier delay line. The TDC is used as a basic building block for time interval measurement in an ultrasonic liquid flowmeter. Operation of the TDC with 10ps LSB resolution and 1 ms input range has been simulated using library models for 1.2 µ m double–metal double–poly CMOS technology. The TDC operates at clock frequency of 200 MHz, and is composed of 500 delay–latch elements. The difference in delay between two chains, one for the start and the other for stop pulse, is controlled by the delay locked loop (DLL). Keywords: Time to digital conversion, Vernier delay line, DLL. 1 Introduction The precise measurement of the time interval between two events with very fine timing resolution is common challenge in the test and measurement instrumentation (logic analyzer, ATE system, nuclear instrumentation), industrial control (multichannel DAS, ultrasonic liquid flowmeters), electronic embedded control system (automotive controllers, medical devices avionics), etc. [1,2,3]. A time–to–digital converter (TDC) is one of the crucial building blocks installed into this type of equipment. High–resolution TDC is primarily used in application...
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...Modelling Of Modern Microprocessors Siddhant (Author) Department of Computer Science Lovely Professional University Phagwara, India siddhant_s@outlook.com Abstract--Microprocessors are also known as a CPU or central processing unit is a complete computation engine that is fabricated on a single chip. The first microprocessor was the Intel 4004, introduced in 1971. This paper covers the evolution in microprocessors and the changes in the architecture of the microprocessor, the details of the latest microprocessors and the machines using them. The paper also discusses how the number of transistors affects the performance of processor. A microprocessor can move data from one memory location to another. A microprocessor can make decisions and jump to a new set of instructions based on those decisions. The native language of a microprocessor is Assembly Language. The above mentioned are the three basic activities of a microprocessor. An extremely simple microprocessor capable of performing the above mentioned operations loos like: Index terms—Modern, architecture, Intel, PC, Apple. I. INTRODUCTION The microprocessor is the heart of any normal computer, whether it is a desktop machine , a server or a laptop . The first microprocessor to make a real splash in the market was the Intel 8088, introduced in 1979 and incorporated into the IBM PC (which first appeared around 1982).The microprocessor is made up of transistors. CHIPA chip...
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...DE09 DIGITALS ELECTRONICS TYPICAL QUESTIONS & ANSWERS PART - I OBJECTIVE TYPE QUESTIONS Each Question carries 2 marks. Choose correct or the best alternative in the following: Q.1 The NAND gate output will be low if the two inputs are (A) 00 (B) 01 (C) 10 (D) 11 Ans: D The NAND gate output will be low if the two inputs are 11 (The Truth Table of NAND gate is shown in Table.1.1) X(Input) Y(Input) F(Output) 0 0 1 0 1 1 1 0 1 1 1 0 Table 1.1 Truth Table for NAND Gate Q.2 What is the binary equivalent of the decimal number 368 (A) 101110000 (B) 110110000 (C) 111010000 (D) 111100000 Ans: A The Binary equivalent of the Decimal number 368 is 101110000 (Conversion from Decimal number to Binary number is given in Table 1.2) 368 184 --- 0 92 --- 0 46 --- 0 23 --- 0 11 --- 1 5 --- 1 2 --- 1 1 --- 0 0 --- 1 Table 1.2 Conversion from Decimal number to Binary number 2 2 2 2 2 2 2 2 2 1 DE09 Q.3 The decimal equivalent of hex number 1A53 is (A) 6793 (B) 6739 (C) 6973 (D) 6379 DIGITALS ELECTRONICS Ans: B The decimal equivalent of Hex Number 1A53 is 6739 (Conversion from Hex Number to Decimal Number is given below) 1 A 5 3 Hexadecimal 16³ 16² 16¹ 16° Weights (1A53)16 = (1X16³) + (10 X 16²) + (5 X 16¹) + (3 X 16º) = 4096 + 2560 + 80 + 3 = 6739 Q.4 (734)8 = ( )16 (A) C 1 D (C) 1 C D Ans: D (734)8 = (1 D C)16 0001 │ 1101 │ 1100 1 D C (B) D C 1 (D) 1 D C Q.5 The simplification of the Boolean expression ABC + A BC is (A) 0 (B) 1 (C) A (D) BC Ans: B ( )( ) The...
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...Encounter® Conformal® Equivalence Checking Reference Manual Conformal ASIC, Conformal Ultra, and Conformal Custom Product Version 9.1 October 2009 © 1997– 2009 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134, USA Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 800.862.4522. Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. All other trademarks are the property of their respective holders. Restricted Print Permission: This publication is protected by copyright and any unauthorized use of this publication may violate copyright, trademark, and other laws. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. This statement grants you permission to print one (1) hard copy of this publication subject to the following conditions: 1. The publication may be used solely for personal, informational, and noncommercial...
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...Programmable Logic Controllers: Programming Methods and Applications by John R. Hackworth and Frederick D. Hackworth, Jr. Table of Contents Chapter 1 - Ladder Diagram Fundamentals Chapter 2 - The Programmable Logic Controller Chapter 3 - Fundamental PLC Programming Chapter 4 - Advanced Programming Techniques Chapter 5 - Mnemonic Programming Code Chapter 6 - Wiring Techniques Chapter 7 - Analog I/O Chapter 8 - Discrete Position Sensors Chapter 9 - Encoders, Transducers, and Advanced Sensors Chapter 10 - Closed Loop and PID Control Chapter 11 - Motor Controls Chapter 12 - System Integrity and Safety Preface Most textbooks related to programmable controllers start with the basics of ladder logic, Boolean algebra, contacts, coils and all the other aspects of learning to program PLCs. However, once they get more deeply into the subject, they generally narrow the field of view to one particular manufacturer's unit (usually one of the more popular brands and models), and concentrate on programming that device with it's capabilities and peculiarities. This is worthwhile if the desire is to learn to program that unit. However, after finishing the PLC course, the student will most likely be employed in a position designing, programming, and maintaining systems using PLCs of another brand or model, or even more likely, many machines with many different brands and models of PLC. It seems to the authors that it would be more advantageous to approach the...
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