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State University of New York at Stony Brook Department of Electrical and Computer Engineering ESE218 Digital Systems Design

Lab 9. Counter design.

1. Objectives - Design of the synchronous finite state machine (FSM) with D-flip-flops and multiplexers - Verification of the circuit behavior with a CAD tool 2. Problem description Design the synchronous 4-bit counter which outputs follow the predetermined repeated sequence of states. The sequence of states represents the sequence of decimal digits of your ID number with the following exceptions: (1) digits which appear more than ones have to be deleted; (2) digit 9 has to be added at the end of the sequence if your ID has no 9. For example, for ID number 105123456 the second 1 and 5 are deleted and 9 is added at the end resulting in sequence 10523469. In the binary form the sequence is shown in Figure 1. The initial state is not critical. State 9 should be decoded to generate special signal SYNC shown in denominator in Figure 1. In the prelab: the circuit behavior has to be verified in OrCAD. The maximum clock frequency has to be calculated using timing specs of the flip-flops and multiplexers (logical gates) from datasheet. In the experiment: first, the functionality of the counter has to be tested with a pushbutton that controls the clock and a 7-segment LED display connected to the outputs. Finally, the counter sequence should be demonstrated with the logic analyzer synchronized with SYNC signal, 4inputs of the logic analyzer should be grouped into a bus. 3. Approaches Outputs of four D-flip-flops Q3Q2Q1Q0 serve as outputs of the counter. Next states Q*3Q*2Q*1Q*0 are formed from present states Q3Q2Q1Q0 with combinational excitation circuits. By design we understand determination of the minimal expressions for combinational circuits which excite flip-flop inputs D3, D2, D1, D0. Next states for unused states should be treated as don’t cares. The state table (Table 1) can be used for find implementations with...

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