where C_gP^* is the gate capacitor per unit width of Mp2, f_cis the carrier frequency (f_c=13.56 MHz), D_effis the effective duty cycle, and W_p is the width of Mp2. Additionally, the optimal size ration for the NMOS and PMOS transistors (Mn1, Mn2, Mp1 and Mp2) has been proven in [2], and van be formed as:
(W_p/W_n )=√((K_n (V_REC-V_(ThN) ))/(K_p (V_REC-|V_(ThP) |) ))
(3.5)
where K_n=μ_n C_ox and K_p=μ_p C_ox, are the transconductances of the NMOS and PMOS, respectively. The main rectifying transistors should have an optimal sizes to minimize the power dissipation depending on f_c and R_L because large transistors will decrease the R_on loss, but it will increase the switching loss. More over large transistors will make an impact on the speed of the comparator due to the gate capacitance [2].
3.3 The Comparator …show more content…
Thus, high power comparator is a tremendous approach to operate a large rectifying transistors at high operating frequency (13.56 MHz) with high operating efficiency, and low power consumption. The turn on and turn off delays of the comparators have an effect on the power efficiency of the rectifier because these delays can cause a reverse current and also affect the switching time of the PMOS transistors. Therefore, the operation of the comparators is controlled by its delay propagation (Tp), which means how speedily the output can behave to a change in the input. Because of that, the comparator has an impact on the power conversion efficiency of the proposed rectifier. The high-to-Low delay propagation (tPHL) of the comparator can turn Mp1 and Mp2 on too late, which means it will minimize the input power that could be transferred to the load. Further, the Low-to-High delay propagation (tPLH) of the comparator may late to turn Mp1 and Mp2 off and make the current goes in a reverse way, which means the current will go back from the load to the input