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80386 Microprocessor

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80386 MICROPROCESSOR It is a 32-bit microprocessor. It has 32 bit data bus and 32 bit address bus, so it can address up to 232 = 4GB of RAM.
Features -Multitasking -Memory management -Software protection -Segmentation and paging -Large memory system(64Tbytes in virtual mode)
Operating modes -Real mode -Protected mode -Virtual mode
Internal architecture: There are 6 parallel functional units:
-The bus unit: The bus interface unit provides a 32-bit data bus, a 32-bit address bus and control signals. 8-bit (byte), 16-bit (word) and 32-bit (double word) data transfers are supported. It has separate pins for its address and data bus lines. This processing unit contains the latches and drivers for the address bus, transceivers for the data bus, and control logic for signaling whether a memory input/output, or interrupt acknowledgement bus cycle is to be performed. -The prefetch unit: The prefetch unit performs a mechanism known as an instruction stream queue. This queue permits a prefetch up to 16 bytes (8 memory words) of instruction code which is used by the instruction decoder. Whenever bytes are loaded into the queue they are automatically shifted up through the FIFO to the empty location near the output. -The decode unit: It reads the machine-code instructions from the output side of the prefetch queue and decodes them into microcode instruction format. The instruction queue, a part of the decode unit permits three fully decoded instructions to be held waiting for use by the execution unit. -The execution unit: The execution unit involves the arithmetic/logic unit-ALU, registers, special multiply, divide, and shift hardware, and a control ROM. The control ROM contains the microcode sequences. The execution unit reads the decoded instructions from the instruction queue and performs the operations that are specified. During the execution of an instruction, it requests the segment and page units to generate operand addresses and the bus interface unit to perform read or write bus cycles to access data in memory or I/O devices.

-The segment unit: It produces a translated linear address which the paging unit translates into the physical address. The instructions requiring memory reference send their request to the segmentation unit for logical unit computation and translation and segment protection violation checking. -The page unit: It translates the linear address generated by prefetch unit to physical address before the prefetch bus cycle request is send to the bus interface unit. It also checks for paging violation.
Pin structure of 80386 MICROPROCESSOR: 80386DX microprocessor is a 132-pin pin grid array. The functions of the 80386 pins are as follows: 1) A31-A2: These are the Address Bus connections used to address any of the 1G*32 memory locations found in the memory system. 2) D31-D0: These are the data bus connections used for the transfer of data between the microprocessor and its memory and the I/O systems. 3): These are the Bank Enable signals used to access a byte, word or a double word data from any of the 4 memory banks. These signals are generated internally by the microprocessor with the help of the least two significant lines of the address bus i.e. A1 and A0.
4) M/: This is a memory or IO status signal. When this is 1, a memory device is selected for memory operation and when it is 0, an IO device is selected for IO operation.
5) W/ : This is write/read control signal. When it is 0, it indicates that the read operation is to be performed and when it is 1, it indicates that write operation is to be performed.
6) : This is the Address Data Strobe signal. It becomes active when a valid IO or memory address is issued by the microprocessor.
7) RESET: This is the Reset signal. When this becomes active, the microprocessor is reset to the real mode causing it to begin execution from the memory location FFFFFFF0 H.
8) CLK2: This is the clock signal. It is driven by a clock signal that is two times the operating frequency of the 80386 microprocessor.
9): This is the READY signal. It controls the number of wait states that are inserted into the timing to control memory access in case of slower peripheral devices.
10) : Lock becomes 0 when an instruction is prefixed by the LOCK prefix. This is mostly used in DMA access.
11) D/ -Data/Control: When this pin is at logic 1, it indicates that the data bus of the microprocessor contains data for or from the memory or IO device. When it is at logic 0, it indicates that the microprocessor is currently halted or executing an interrupt acknowledge.
12) - Bus size 16: When this pin is at logic 1, it selects a 32 bit data bus and when it is at logic 0, it selects a 16 bit data bus.
13) -Next Address: This pin causes the microprocessor to output the address of the next instruction data in the current bus cycle. This pin is used at the time of pipe-lining.
14) HOLD: This signal requests a DMA action.
15) HLDA – Hold Acknowledge: It indicates that 80386 is currently in the hold state.
16) - Coprocessor request: This signal asks the 80386 microprocessor to release the control and is a direct connection to the 80387 arithmetic coprocessor.
17) : This is an input signal that is used by the WAIT and FWAIT instructions that wait for the coprocessor to become not busy. This is also a direct connection to the 80387 arithmetic coprocessor from 80386 microprocessor.
18) : This pin indicates to the microprocessor that an error has been detected by the coprocessor.
19) INTR – Interrupt request : This pin is used by the external circuitry to request an interrupt.
20) NMI –Non-Maskable Interrupt: This pin requests a non-maskable interrupt.

ADDRESSING MODES: The data addressing modes of 80386 microprocessor are as follows: 1) Register Addressing: The operands in the instructions are registers or memory locations. These registers may be 16-bit or 32-bit. Eg: MOV CX, DX – This instruction transfers a word from source register DX to destination register CX. 2) Immediate Addressing: The operand is an immediate byte or word of data. The data may also be a double-word.
Eg: MOV EAX, FFFFFFFFH – This instruction transfers the double-word immediate data FFFFFFFFH to the 32-bit wide register EAX. 3) Direct Addressing: The operand is a memory address that is in the data segment. This memory location may be word-sized or double word-sized. Eg: MOV EAX, LOC – This instruction copies the double word contents of memory address LOC in the data segment into EAX. 4) Register Indirect Addressing : A memory location is addressed by an index or base register. These index and base registers are BP,BX,DI,SI and their extended versions. Eg: If the contents of the register BX are 1234H,then the instruction MOV AX,[BX] copies the contents the data segment memory offset address 1234H into the register AX. 5) Base-Plus-Index Addressing: The operand is a memory location that is addressed by a base register plus an index register. The base register may be like BP or BX and the index register may be like SI,DI and their extended versions. Eg: MOV CL,[EDX+EDI] –This instruction copies the byte contents of the memory location addressed by EDX plus EDI into register CL. 6) Register Relative Addressing: The operand is a memory location that is addressed by an index or base register plus displacement. 7) Eg: The instruction MOV AX,[DI+100H] copies the word contents of the data segment memory location that is addressed by DI plus 100H into register AX. 8) Base Relative-Plus-Plus-Index Addressing: The operand is a memory location that is addressed by a base and an index register plus displacement. 9) Eg: The instruction MOV AX,[BX+DI+4] copies a word of data from a memory location addressed by the sum of BX,DI and 4 into the register AX. 10) Scaled-Index Addressing: Here, the operand memory address is generated by the second register multiplied by a scaling factor. This kind of addressing uses two 2-bit registers. Eg: MOV AL,[EAX+4*EBX] instruction copies byte-sized contents of the data segment memory location that is addressed by EAX plus 4 times EBX into the register AL.The scaling factor may be 2,4,8 to access a word, a double-word or a quad-word memory array data.

Register Structure:

1)General purpose registers: -EAX(Accumulator) [AX, AH, AL]: It holds the temporary results after an arithmetic and logic operation. -EBX(Base Register)[BX, BH, BL]: It holds the offset address of a location in memory system. - ECX(Count)[CX,CH,CL]: It holds the counts for the various instructions and can also hold the offset address of a memory data. Used in repeated string instructions, shift, rotate, loop. -EDX(Data)[DX, DH, DL]: It holds the part of the result from a multiplication or a part of the dividend before a division. -EBP(Base Pointer)[BP]: It points to the 16 bit or 32 bit memory location. -EDI(Destination Index)[DI] : Addresses the string destination data for string instructions. -ESI(Source Index)[SI]: It addresses the source string data for string instructions.
2)Special Purpose Registers: -EIP(Instruction pointer)[IP]: The instruction pointer points to the next instruction in the program located within the code segment. -ESP(Stack Pointer)[SP]: It addresses an area of memory called the stack. The stack memory stores the data using this pointer. -EFLAGS(Flag register)[FLAGS]: -C(Carry Flag): This holds the carry after addition or borrow after subtraction. It also indicates the error condition dictated by some programs and procedures. -P(Parity Flag): P=0 for odd parity and P=1 for even parity. -A(Auxiliary Carry): it holds the carry after addition or borrow after subraction between bits 3 and 4 of the result. -Z(Zero Flag): Z=1 if the result is zero and Z=0 otherwise after the arithmetic or logic operations. -S(Sign flag): If S=1 the sign bit is set or negative. If S=0 the sign bit is cleared or positive after the execution of arithmetic and logic instructions. -T(Trap): The trap flag enables the trapping through an on-chip debugging feature. If T=0 the trap is disabled. -I(Interrupt): If I=1 the INTR pin is enabled. If I=0 the INTR pin is disabled. -D(Direction): If D=1 the registers are automatically decremented. If D=0 the registers are automatically incremented. -O(Overflow): O=1 indicates that an overflow has occurred when signed numbers are added or subtracted. For unsigned operations, the overflow flag is ignored. -IOPL(I/O Privilege level): it is used in protected mode operation to select the privilege level for I/O devices.00 is the highest or most trusted and 11 is the lowest or least trusted. -NT(Nested task): It indicates that the current task is nested within another task in protected mode of operation. -RF(resume): This flag is used with debugging to control the resumption of execution after the next instruction. -VM(Virtual Mode): This flag bit selects the virtual mode operation in protected mode system.
3)Segment registers: -CS(Code): In real mode operation, it defines the start of 64KB memory. In protected mode,it selects a descriptor that describes the starting address and length of a section of memory holding code. -DS(Data): The data segment is a section of the memory that contains most data used by a program which can be accessed by an offset address. -ES(Extra): This is an additional data segment used by some of the string instructions to hold destination data. -SS(Stack): The stack segment defines the area of memory used for the stack. The location of the most accessible element is determined by the stack pointer register and the BP register. -FS and GS: The FS and GS segments are the supplemental segment registers available in 80386. They allow 2 additional memory segments for acces by programs.
4)Control Registers: There are three Control registers CR0,CR2 & CR3.

(CR1 is left undefined by Intel). (I)CR0: (MSW- Machine Status Word) 0. PE: (Protection Enable) If PE=1-protected mode, PE=0 real-address mode. 1. MP: (Math Present): If set assumes that the arithmetic coprocessor is attached.
2. EM: (Emulate Co-processor) this bit is set to cause a type 7 interrupt for each ESC instruction
3. TS: (Task Switched): It indicates 80386 has switched tasks in protected mode.
4. ET: (Extension type) ET indicates the type of coprocessor present in the system (80287 if ET=0 or 80387 if ET=1).
5 .PG: (Paging) When set enables paging and if reset disables paging in MMU.
(II)CR2: It holds the linear page address of the last page accessed before a page fault interrupt. (III)CR3: It holds the base address of the page directory.
5) Debug and Test Registers:
There are 8 debug registers for hardware debugging. Out of these DR0 to DR7, two registers DR4 and DR5 are Intel reserved.DR0 to DR3 store four program controllable breakpoint addresses. DR6 and DR7 respectively hold breakpoint status and breakpoint control information. There are two test registers TR6 and TR7.The test registers are used to perform confidence checking on the paging MMU’s translation look aside buffer (TLB).By writing into this register one can initiate write directly into 80386 TLB or perform a mock TLB lookup. TR6 is test command register and TR7 is test data register.

Software models of 80386:
1) Real mode: After reset, the 80386 starts from memory location FFFFFFF0H under the real address mode. In real mode, the default operand size is 16 bits but 32- bit operands and addressing modes may be used with the help of override prefixes. Real mode Operation allows microprocessor to address only first 1M of memory using address lines A0-A19.The segment size in real mode is 64k, hence the 32-bit effective addressing must be less than 0000FFFFFH. Segments and offset: A combination of a segment address and an offset access a memory location in the real mode. The segment address is located within one of the segment registers which defines the beginning address. The offset address selects any location within 64Kbyte Memory segment. If segment register contains 1000H, but the starting address of the segment is taken as 10000H. In real mode each segment is internally appended with 0H on its rightmost end. This forms a 20 bit memory address. Because of internally appending 0 real mode segments can only begin at a 16-byte boundary in the memory system, this 16-byte boundary is called paragraph.

The segments in 80386 real mode may be overlapped or non-overlapped. The interrupt vector table of 80386 has been allocated 1Kbyte space starting from 00000H to 003FFH.

2)Protected mode: Protected mode memory addressing allows access to data and program located above the first 1M byte as well as within the first 1M byte of memory. No segment address is present in protected mode as it was in the real mode, instead the segment register contains a selector that selects a descriptor from the descriptor table. The descriptor table describes the memory segment’s location, length and access rights. The paging unit is a memory management unit enabled only in protected mode. The paging mechanism allows handling of large segments of memory in terms of pages of 4Kbyte size. -Selectors and descriptors: The selector is located in segment register which selects one of the 8192 descriptors from one of two tables of descriptors. There are two descriptor tables used with the segment registers: one contains global descriptors and other contains local descriptors. The global descriptors contain the segment definition that applies to all programs while the local descriptors are usually unique to an application. Each descriptor table contains 8192 descriptors, so total 16,384 descriptors are available to an application at a time. -Descriptor Tables: There are 3 types of the 80386 descriptor tables are listed as follows: •Global Descriptor Table (GDT) •Local Descriptor Table (LDT) •Interrupt Descriptor Table (IDT) -Descriptors: The 80386 descriptors have a 20-bit segment limit and 32-bit segment address. The descriptors of 80386 are 8-byte quantities having access rights or attribute bits along with the base and limit of the segments. -Base (B31-B0): It defines the starting 32 bit address of the segment within the 4GB physical address space. -Limit (L19-L0): It defines the limit of the segment in units of bytes, if G=0 else in units of 4KB if G=1. -Access Rights: it determines the privilege level and other information about the segment. -Descriptor Attribute Bits: -The D bit specifies the code segment operation size. If D=1, the segment is a 32-bit operand segment, else, it is a 16-bit operand segment. -The G (granularity): If G=0, the limit specifies the segment limit of 1 to 1 Mbyte in length as the limit is 20 bit long. If G=1, the limit is appended by 000H. This allows the segment length to be of 4 Kbytes to 4GB. -The AVL (available) bit specifies whether the descriptor is available for user (AVL=1) or not (AVL=0).
The 80386 has five types of descriptors listed as follows:
1. Code or Data Segment Descriptors.
2. System Descriptors.
3. Local descriptors.
4. TSS (Task State Segment) Descriptors.
5. GATE Descriptors.
The 80386 provides a four level protection mechanism exactly in the same way as the
80286 does.

PAGING OPERATION:
Paging is one of the memory management techniques used for virtual memory multitasking operating system. The segmentation scheme may divide the physical memory into a variable size segments but the paging divides the memory into a fixed size pages. The segments are supposed to be the logical segments of the program, but the pages do not have any logical relation with the program. The pages are just fixed size portions of the program module or data. The advantage of paging scheme is that the complete segment of a task need not be in the physical memory at any time. Only a few pages of the segments, which are required currently for the execution, need to be available in the physical memory. Thus the memory requirement of the task is substantially reduced, relinquishing the available memory for other tasks. Whenever the other pages of task are required for execution, they may be fetched from the secondary storage. The previous page which is executed need not be available in the memory, and hence the space occupied by them may be relinquished for other tasks. Thus paging mechanism provides an effective technique to manage the physical memory for multitasking systems.
-Paging Unit: The paging unit of 80386 uses a two level table mechanism to convert a linear address provided by segmentation unit into physical addresses.

The paging unit converts the complete map of a task into pages, each of size 4K. The task is further handled in terms of its page, rather than segments. The paging unit handles every task in terms of three components namely page directory, page tables and page itself.
-Paging Descriptor Base Register: The CR3 is used as page directory physical base address register, to store the physical starting address of the page directory. The lower 12 bits of the CR3 are always zero to ensure the page size aligned directory. A move operation to CR3 automatically loads the page table entry caches and a task switch operation, to load CR0 suitably.
-Page Directory: This is at the most 4Kbytes in size. Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a directory. The upper 10 bits of the linear address are used as an index to the corresponding page directory entry. The page directory entries point to page tables.
-Page Tables: Each page table is of 4Kbytes in size and many contain a maximum of
1024 entries. The page table entries contain the starting address of the page and the statistical information about the page. The upper 20 bit page frame address is combined with the lower 12 bit of the linear address. The address bits A12- A21 are used to select the 1024 page table entries. The page table can be shared between the tasks.
•The P bit of the above entries indicates if the entry can be used in address translation.
•If P=1, the entry can be used in address translation, otherwise it cannot be used.
•The P bit of the currently executed page is always high.
•The accessed bit A is set by 80386 before any access to the page. If A=1, the page is accessed, else unaccessed.
•The D bit (Dirty bit) is set before a write operation to the page is carried out. The D-bit is undefined for page director entries.
•The OS reserved bits are defined by the operating system software.
•The User / Supervisor (U/S) bit and read/write bit are used to provide protection. These bits are decoded to provide protection under the 4 level protection model.
•The level 0 is supposed to have the highest privilege, while the level 3 is supposed to have the least privilege.
•This protection provide by the paging unit is transparent to the segmentation unit.

Virtual Mode
In its protected mode of operation, 80386DX provides a virtual 8086 operating environment to execute the 8086 programs. The real mode can also used to execute the 8086 programs along with the capabilities of 80386, like protection and a few additional instructions.
Once the 80386 enters the protected mode from the real mode, it cannot return back to the real mode without a reset operation. Thus, the virtual 8086 mode of operation of 80386, offers an advantage of executing 8086 programs while in protected mode. The address forming mechanism in virtual 8086 mode is exactly identical with that of 8086 real mode. In virtual mode, 8086 can address 1Mbytes of physical memory that may be anywhere in the 4Gbytes address space of the protected mode of 80386.Like 80386 real mode, the addresses in virtual 8086 mode lie within 1Mbytes of memory. In virtual mode, the paging mechanism and protection capabilities are available at the service of the programmers. The 80386 supports multiprogramming, hence more than one programmer may use the CPU at a time. Paging unit may not be necessarily enable in virtual mode, but may be needed to run the 8086 programs which require more than 1Mbyts of memory for memory management function. In virtual mode, the paging unit allows only 256 pages, each of 4Kbytes size. Each of the pages may be located anywhere in the maximum 4Gbytes physical memory. The virtual mode allows the multiprogramming of 8086 applications. The virtual 8086 mode executes all the programs at privilege level 3.Any of the other programmes may deny access to the virtual mode programs or data. However, the real mode programs are executed at the highest privilege level, i.e. level 0. The virtual mode may be entered using an IRET instruction at CPL=0 or a task switch at any CPL, executing any task whose TSS is having a flag image with VM flag set to 1. The IRET instruction may be used to set the VM flag and consequently enter the virtual mode. The PUSHF and POPF instructions are unable to read or set the VM bit, as they do not access it. Even in the virtual mode, all the interrupts and exceptions are handled by the protected mode interrupt handler. To return to the protected mode from the virtual mode, any interrupt or execution may be used. As a part of interrupt service routine, the VM bit may be reset to zero to pull back the 80386 into protected mode. Instruction Set: 1) Data movement instructions | mov reg, reg1mov mem/reg, regmov reg, memmov mem/reg, datamov ax/al, memmov mem, ax/almov segreg, mem16/ reg16 mov mem16/reg16, segreg | Moves (copies) data of source (2nd argument) to the destination (1st argument). No memory to memory move operation. | | xchg op1, op2 | The xchg (exchange) instruction swaps two values | | LxS dest, sourcelds/les/lfs/lgs/lss reg16, mem32 | Load 32 bit double word at the address specified by mem32 into reg16 and the ds, es, fs, gs, or ss registers. general purpose register=L.O. wordsegment register =H.O. word | | lea dest, sourcelea reg16, memlea reg32, mem | Loads the specified 16 or 32 bit general purpose register with the effective address of the specified memory location. The effective address is the final memory address obtained after all addressing mode computations. | | push reg16/reg32pop reg16/reg32 push segregpop segreg (except CS)push/pop memorypushad popad pushf popfpushfd popfd | The push instructions move data onto the hardware stack and the pop instructions move data from the stack to memory or to a register. Pushf and pushfd push the flags onto the stack. | | sahflah | lahf - load ah from flagssahf -store ah into flags | 2) Conversions | movzx dest, srcmovsx dest, srccbw cwdcwde cdqbswap reg32xlat | These instructions sign or zeroextend values, the last two convert between storage formats and translate values via alookup table | 3) Arithmetic instructions | add dest, srcadc dest, src SUB dest, src sbb dest, src mul src imul src acc= acc*srcimul dest, src1, imm_src imul dest, imm_src div src cmp dest, src neg dest inc dest dec dest xadd dest, srccmpxchg operand1, operand2 cmpxchg8ax, operand aaa aadaam aasdaa das | Add: dest := dest + srcAdc: dest := dest + src + CSub: dest := dest – srcSbb: dest := dest - src - CMul: acc := acc * srcImul: dest := src1 * imm_src dest := dest * imm_srcdiv: acc := xacc /-mod srccmp: dest - src (and set flags)neg: dest := - destinc: dest := dest + 1dec: dest := dest – 1aaa -ASCII adjust after additiondaa - decimal adjust for addition | 4)Logical operations | and dest, source or dest, source xor dest, source not dest | And: dest := dest and sourceOr: dest := dest or sourceXor: dest := dest xor sourceNot: dest := not dest | 5)The Shift Instructions | Shl/sal/shr/sar dest, countshld dest, source, count | shl (shift left) sal (shift arithmetic left) shr (shift right)sar (shift arithmetic right) | 6)The Rotate Instructions | Rcl/rol/rcr/ror dest, count | rcl (rotate through carry left)rcr (rotate through carry right)rol (rotate left)ror (rotate right). | 7) The Bit Operations | test dest, sourcebt/btc/btr/bts source, indexbsf/bsr dest, source | there are instructions to test bitswithin an operand, to test and set, clear, or invert specific bits in an operand, and to searchfor set bits | 8)I/O operations | in eax/ax/al, port/dxout port/dx, eax/ax/al | In: Read portOut: Write data in reg to port. | 9) String Instructions | movs {b,w,d} lods {b,w,d} stos {b,w,d} scas {b,w,d}cmps {b,w,d} ins {b,w,d} outs{b,w,d} rep{b,w,d} repz{b,w,d} repe{b,w,d} repnz{b,w,d} repne {b,w,d} | Movs: Move stringLods: Load string element into the accumulatorStos: Store accumulator into string elementScas: Scan string and check for match against the value in the accumulatorCmps: compare two stringsIns: input a string from an I/O portOuts: output a string to an I/O portRep: repeat a string operationRepz: repeat while zeroRepe: repeat while equalRepnz: repeat while not zeroRepne: repeat while not equal | 10)The CALL and RET Instructions | call disp16/adrs32/mem16/ reg16/mem32ret retn retf ret disp retn disp retf disp | The call and ret instructions handle subroutine calls and returns. | 11)Miscellaneous Instructions | clc | Clears the carry flag | | stc | Sets the carry flag | | cmc | Complements the carry flag | | cld | Clears the direction flag | | std | Sets the direction flag | | cli | Clears the interrupt enable/disable flag | | sti | Sets the interrupt enable/disable flag |

SET AND CONDITIONAL JUMP Instructions Instruction | Description | Condition | SETC/JC | Set/jump if carry | Carry = 1 | SETNC/JNC | Set/jump if no carry | Carry = 0 | SETZ/JZ | Set/jump if zero | Zero = 1 | SETNZ/JNZ | Set/jump if not zero | Zero = 0 | SETS/JS | Set/jump if sign | Sign = 1 | SETNS/JNS | Set/jump if no sign | Sign = 0 | SETO/JO | Set/jump if overflow | Ovrflw=1 | SETNO/JNO | Set/jump if no overflow | Ovrflw=0 | SETP/JP | Set/jump if parity | Parity = 1 | SETPE/JPE | Set/jump if parity even | Parity = 1 | SETNP/JNP | Set/jump if no parity | Parity = 0 | SETPO/JPO | Set/jump if parity odd | Parity = 0 |…...

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