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# Asic

Submitted By Arunabi
Words 788
Pages 4
SNUG-2000
San Jose, CA
Voted Best Paper
1st Place

World Class Verilog & SystemVerilog Training

Nonblocking Assignments in Verilog Synthesis, Coding
Styles That Kill!

Clifford E. Cummings
Sunburst Design, Inc. cliffc@sunburst-design.com www.sunburst-design.com

ABSTRACT
One of the most misunderstood constructs in the Verilog language is the nonblocking assignment. Even very experienced Verilog designers do not fully understand how nonblocking assignments are scheduled in an IEEE compliant Verilog simulator and do not understand when and why nonblocking assignments should be used. This paper details how Verilog blocking and nonblocking assignments are scheduled, gives important coding guidelines to infer correct synthesizable logic and details coding styles to avoid Verilog simulation race conditions.

1.0 Introduction
Two well known Verilog coding guidelines for modeling logic are:

Guideline: Use blocking assignments in always blocks that are written to generate combinational logic [1].
Guideline: Use nonblocking assignments in always blocks that are written to generate sequential logic [1].

But why? In general, the answer is simulation related. Ignoring the above guidelines can still infer the correct synthesized logic, but the pre-synthesis simulation might not match the behavior of the synthesized circuit.
To understand the reasons behind the above guidelines, one needs to have a full understanding of the functionality and scheduling of Verilog blocking and nonblocking assignments. This paper will detail the functionality and scheduling of blocking and nonblocking assignments.
Throughout this paper, the following abbreviations will be used:
RHS - the expression or variable on the right-hand-side of an equation will be abbreviated as
RHS equation, RHS expression or RHS variable.
LHS - the expression or variable on the left-hand-side of an equation will be abbreviated as LHS equation, LHS expression or LHS variable.

2.0 Verilog race conditions
The IEEE Verilog Standard [2] defines: which statements have a guaranteed order of execution
("Determinism", section 5.4.1), and which statements do not have a guaranteed order of execution ("Nondeterminism", section 5.4.2 & "Race conditions", section 5.5).
A Verilog race condition occurs when two or more statements that are scheduled to execute in the same simulation time-step, would give different results when the order of statement execution is changed, as permitted by the IEEE Verilog Standard.
To avoid race conditions, it is important to understand the scheduling of Verilog blocking and nonblocking assignments.

SNUG San Jose 2000
Rev 1.3

2

Nonblocking Assignments In Verilog
Synthesis, Coding Styles that Kill

3.0 Blocking assignments
The blocking assignment operator is an equal sign ("="). A blocking assignment gets its name because a blocking assignment must evaluate the RHS arguments and complete the assignment without interruption from any other Verilog statement. The assignment is said to "block" other assignments until the current assignment has completed. The one exception is a blocking assignment with timing delays on the RHS of the blocking operator, which is considered to be a poor coding style [3].
Execution of blocking assignments can be viewed as a one-step process:
1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side expression) of the blocking assignment without interruption from any other Verilog statement.
A blocking assignment "blocks" trailing assignments in the same always block from occurring until after the current assignment has been completed
A problem with blocking assignments occurs when the RHS variable of one assignment in one procedural block is also the LHS variable of another assignment in another procedural block and both equations are scheduled to execute in the same simulation time step, such as on the same clock edge. If blocking assignments are not properly ordered, a race condition can occur. When blocking assignments are scheduled to execute in the same time step, the order execution is unknown. To illustrate this point, look at the Verilog code in Example 1. module fbosc1 (y1, y2, clk, rst); output y1, y2; input clk, rst; reg y1, y2; always @(posedge clk or posedge rst) if (rst) y1 = 0; // reset else y1 = y2; always @(posedge clk or posedge rst) if (rst) y2 = 1; // preset else y2 = y1; endmodule Example 1 - Feedback oscillator with blocking assignments

According to the IEEE Verilog Standard, the two always blocks can be scheduled in any order. If the first always block executes first after a reset, both y1 and y2 will take on the value of 1. If the second always block executes first after a reset, both y1 and y2 will take on the value 0. This clearly represents a Verilog race condition.

SNUG San Jose 2000
Rev 1.3

3

Nonblocking Assignments In Verilog
Synthesis, Coding Styles that Kill

4.0 Nonblocking assignments
The nonblocking assignment operator is the same as the less-than-or-equal-to operator ("

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