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Comparator Design

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Comparator Design
For the comparator, we use the fully dynamic comparator (StrongArm) configuration. For minimum area and power, we use minimum sized transistors for the latch as long as the specs are met.

Offset calculation:
For minimum size device, ΔVth is approximately = 0.1tox/√(WL) = 0.1*23.3/√(0.12*0.1)=21mV.
Voffset at the input = ΔVth,M1:M2 + ΔVth,M3:M4/(2Vth/V*) + ΔVth,M1:M2/(2Vth/V*)^2 where Vth is about 200mV and V* is about 80mV. The pre-charged transistors do not contribute to the offset since they are just acting as switches (i.e their Vth’s do not matter).
Thus Vio, comparator = 21 + 21/(400/80) + 21/(400/80)^2 = 26 mV < 50mV. The spec is met.
Overclocked recovery test:
We applied a differential input of 1.2V and an input of -1mV in sequence. The following graph shows that the latch operates correctly.

Regenerative gain:
The following graph shows the regenerative gain for three temperatures. The worst case gain happens at the highest temperature T= 120°C

The slope of the regenerative gain graph in dB scale is given by 20*(log e)/Ts where Ts = CL/gm where gm is the gm of the inverter pair ≈ 100u and CL = 10f.
Slope in logscale = 20*(log e)*100u/10f = 86.8 dB per 1ns which is close to the simulation results.

Total Integrated Noise at output:
The following graph shows the total integrated noise at the output over time for three temperatures. The worst case happens at the highest temperature T=120

The following graph shows the noise contribution by devices

Calculated noise variance is approximately:
= 8kT*gm1/C1(Vth/Id)*(gm1*Vth/Id)2
= 8kT/C1(2Vth/V*)(2Vth/V*)^2 = 8kT/C1(2Vth/V*)3 = (8*4.14x10^-21*/2.064f)*125=0.002 which is about what we get in simulation where C1 = Cgd1 + Cdb1 + Cgd,clk + Cdb,clk + Cgs3= 2.064fF

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