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Computer Architecture

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Cache Memory
[pic]
– Study of large program reveal that most of the execution time is spend, in the execution of a few routines (sub-sections). When the execution is localized within these routines, a number of instructions are executed repeatedly, This property of programs is known as LOCALITY OF REFERENCE. – Thus while some localized area of the program are executed repeatedly, the other areas are executed less frequently. – To reduce the execution time these most repeated segments may be placed in a fast memory known as CACHE (or Buffer) Memory. – The memory control circuitry is designed to take advantage of the property of LOCALITY OF REFERENCE. – If a word in a block of memory is read, that block is transferred to one of the slots of the cache.

Cache Operation: – CPU requests contents of memory location – Check cache for this data – If present, get from cache (fast) – If not present, read required block from main memory to cache – Then deliver from cache to CPU – Cache includes tags to identify which block of main memory is in each cache slot [pic]

[pic]
[pic]
Fig: Cache Organization

Elements of Cache Design:
Cache Size
Write Policy
Replacement Algorithm
Mapping Function
Block Size / Line Size

CACHE SIZE: – Size of cache should be small enough so that average cost per bit is close to that of main memory and large enough so that average access time is close to that of a cache alone. – The larger the cache, the larger the number of gates involved in addressing the cache, so large cache tend to be slightly slower than smaller ones. – In a system with n address lines, Main memory consists of 2n addressable words. – Cache is divided in to m lines of k words size – Main memory will consists of M = 2n/k blocks – Since number of lines is considerably less than the number of main memory blocks m

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