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# Cryptography

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EC6020 – ARSITEKTUR KOMPUTER LANJUT

TUGAS – 4

CHAPTER 5 BUS, CACHE AND SHARED MEMORY

SOAL-SOAL TENTANG ORGANISASI-ORGANISASI CACHE MEMORY (CACHE MEMORY ORGANIZATIONS)

ARWIN NIM. 232 06 008

MAGISTER TEKNIK ELEKTRO SEKOLAH TINGGI ELEKTRONIKA DAN INFORMATIKA INSTITUT TEKNOLOGI BANDUNG 2006

1

Problem 5.8 – The main memory of a computer is organized as 64 blocks with a block size of eight (8) words. The cache has eight (8) block frames. In parts (a) through (d), show the mapping from the numbered blocks in main memory to the block frames in the cache. Draw all lines showing the mappings as clearly as possible.

a.

Show the direct mapping and the address bits that identify the tag field, the block

number, and the word number. b. Show the fully associative mapping and the address bits that identify the tag field and the

word number. c. Show the two-way set-associativity mapping and the address bits that identify the tag

field, the set number, and the word number. d. Show the sector mapping with four blocks per sector and the address bits that identify

the sector number, the block number, and the word number

From the above statement, we get the memory and cache configuration information to calculate the identification bits and the addressing scheme. They are : Main memory has 64 blocks → n = 64 Cache memory has 8 block frames → Block size is 8 words → b = 8

↔ s = 6 because n = 2 s m = 8 ↔ r = 3 because m = 2r

↔ w = 3 because b = 2w

a.

Direct mapping cache Tag field = s − r = 6 − 3 = 3 bit Block field = r = 3 bit Word field = w = 3 bit

Arwin – 23206008@2006

2

The addressing and mapping scheme are as followed :

Arwin – 23206008@2006

3

b.

8-way Fully associativity cache Tag field = s = 6 bit Word field = w = 3 bit

The addressing and mapping scheme are as followed :

Arwin – 23206008@2006

4

c.

2-way Set associativity cache Set = v = 4

↔ d = 2 because v = 2d

Tag field = s − d = 6 − 2 = 4 bit Set field = d = 2 Word field = w = 3 bit

For 2-way associativity cache implementation, there will be 4 sets where each set consists of 2 block frames (subsets) and each subset will cover 2 main memory blocks. The 4-bit tag

determines which 2 main memory’s blocks have right access to a particular set at a time (see the table below).

Set Number (2 bits) 0 (00) 1 (01) 2 (10) 3 (11) 0 (00) 1 (01) 2 (10) 3 (11) 0 (00) 1 (01) 2 (10) 3 (11) 0 (00) 1 (01) 2 (10) 3 (11)

Block Frame Number

Memory Block Number (2-way associativity) 0, 16 and 32, 48 1, 17 and 33, 49 2, 18 and 34, 50 3, 19 and 35, 51 4, 20 and 36, 52 5, 21 and 37, 53 6, 22 and 38, 54 7, 23 and 39, 55 8, 24 and 40, 56 9, 25 and 41, 57 10, 26 and 42, 58 11, 27 and 43, 59 12, 28 and 44, 60 13, 29 and 45, 61 14, 30 and 46, 62 15, 31 and 47, 63

B0 dan B1
B2 dan B3

B4 dan B5 B6 dan B7 B0 dan B1 B2 dan B3

B4 dan B5
B6 dan B7 B0 dan B1 B2 dan B3 B4 dan B5 B6 dan B7 B0 dan B1

B2 dan B3
B4 dan B5 B6 dan B7

Arwin – 23206008@2006

5

The addressing and mapping scheme are as followed :

Arwin – 23206008@2006

6

d.

4-block Sector cache

64 memory’s blocks are divided into 16 sectors which each sector contains 4 blocks. 8 cache’s block frames are divided into 2 sectors which each sector contains 4 block frames. Block field = 4 bits to cover 16 sectors of the main memory. Tag field = 3 bits which is divided into 2 functions, selection bit and sector bit.

Sector Number (1 bit) 0 1 0 1

Block Frame Number

Sector Number

MemoryBlock Number

B0 dan B3 B4 dan B7 B0 dan B3 B4 dan B7

0,1, .......,15

B0 , B1 , ..........., B63

0,1, .......,15

B0 , B1 , ..........., B63

The addressing and mapping scheme are as followed :

Arwin – 23206008@2006

7

This 4-block sector mapping scheme allows each memory’s sector placed in any of the available cache’s block frames in fully associative mode.

Arwin – 23206008@2006

8

Problem 5.9 – Consider a cache characteristics :

( M1 )

and memory

( M2 )

hierarchy with the following

M 1 : 16 Kwords, 50 ns access time. M 2 : 1 Mwords, 400 ns access time.
Assume eight-word cache blocks and a set size of 256 words with set-associative mapping.

a. b.

Show the mapping between M 2 and M 1 . Calculate the effective memory access time with a cache hit ratio of h = 0.95 .

a.

Mapping between M 2 and M 1 .

From the above statement we collect some

information such that : 1 block = 8 word → b = 23 16 Kwords cache

↔ w = 3.

= m ↔ m = 214 words = 214− 3 = 211 block frames or

2, 048 block frames starting from B0 − B2,047 . So that r = 11 bits.
1 Mwords memory = n

↔ n = 220 words = 220− 3 = 217 memory blocks or

131, 072 blocks starting from B0 − B131,071 . So that s = 17 bits.
Set size, k = 256 = 28 words or k = 28− 3 = 25 blocks. There will be 32-way associativity. Then, number of sets, v =

m 211 = = 26 or 64 sets starting from k 25

S0 − S63 .

Hence, each set will consist of 32 block frames. The bit set number,

d = log 2 v = 6 bits.
Word field = 3 bits. Set field = 6 bits to cover 64 sets of the cache memory. Tag field = s − d = 17 − 6 = 11 bits.

Arwin – 23206008@2006

9

Mapping Table

Set Number (6 bits)

Block Frame Number

Memory Block Number (32-way associativity)

0 (000000)

B0 , B1 , ......., B32

0, 64, 128, ……, 131008

1 (000001)

B33 , B34 , ......., B63

1, 65, 129, ……, 131009

2 (000010)

B64 , B65 , ......., B95

2, 66, 130, ……, 131010

3 (000011)

B96 , B65 , ......., B127

3, 67, 131, ……, 131011

…………..

………….

……………….

36 (100100)

B1152 , B65 , ......., B1183

36, 100, 167, ……, 131047

…………..

………….

……………….

63 (111111)

B2016 , B65 , ......., B2047

63, 127, 191, ……, 131071

Arwin – 23206008@2006

10

The mapping scheme is as followed :

Arwin – 23206008@2006

11

b.

The effective memory-access time can be derived as followed :

The general formula for effective memory-access time is :

Teff = ∑ f i .t i where n is nth -memory hierarchy. i =1

n

Because f i = (1 − h1 )(1 − h2 ) ........ (1 − hi −1 ) hi , the above formula can be rewritten as

Teff = h1t1 + (1 − h1 ) h2 t 2 + ............ + (1 − h1 ) h2 t 2 ....... (1 − hn −1 ) t n

What we’ve got are : Cache ( M 1 ) access time, t1 = 50 ns Memory ( M 2 ) access time, t 2 = 400 ns Cache hit ratio, h1 = 0.95 and the access to the outermost memory, M 2 , is always hit or h2 = 1

So, the effective memory-access time is :

Teff = h1 t1 + (1 − h1 ) h2 t 2 = ( 0.95 )( 50 ) + (1 − 0.95 )(1)( 400 ) = 47.5 + 20 = 67.5 ns

Arwin – 23206008@2006

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