Chapter 1
Introduction
This experiment requires students to design and implement a digital clock on DE1 board using Verilog HDL language. In this experiment, the digital clock was deigned to have four functions. As shown below, three of them are fundamental functions and one is additional function. Fundamental functions:
• 4-digit minute and second display
• Time setting.
• A stopwatch with 4-digit second and tenth of a second display
Additional function:
• Alarm
DE1 package In this experiment, DE1 packages were provided for the students. The components in the package are shown below, in which the DE1 board and the USB cable were mainly used.
Figure 1.1: The DE1 package
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DE1 board Figure 1.2 shows the configuration of DE1 board. The 7-seg display mudule was used to display the clock. All red LEDs were used in the alarm function. The digital clock also uses 6 switches and 4 buttons. Their functions are indicated below. sw1: sw2: sw3: sw4: sw5: sw6: button 0-3:
clear set show alarm alarm on show stopwatch stopwatch start add one
Figure 1.2: The DE1 board
Quartus II Quartus II is the software used to program in this experiment.
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Chapter 2
Methodology
The procedure of the experiment can be divided into seven steps as indicated below.
1. write the Verilog code
2. create the symbol
3. use vector waveform simulate the input and output
4. design block diagram
5. compilation
6. connect the DE1 board and assign the pins
7. carry out the program
In the following sections, the methodology in first 4 steps will be introduced in detail.
2.1
2.1.1
Verilog code
Frequency divider
Frequency divider is designed to generate 1 Hz and 100 Hz clock pulses. The 1 Hz clock signal is for clock mode and the 100 Hz one is for stopwatch mode. The DE1 board includes three oscillators that produce 27 MHz, 24 MHz, and 50 MHz clock signals. In this experiment, the 27 MHz oscillator was used. Therefore, in clock mode, the divider needs to generate one pulse every time it receives 27000000 clock signals. In stopwatch mode, one pulse is generated every time 270000 clock signals have been received. The code for the frequency divider is shown below.
From Listing 2.1, this module includes two inputs and one output. The input clock is connected to the 27 MHz oscillator. The input stw on is used to switch the mode. The output clkpulse sends out the generated clock signal. Besides, a variable in type of integer
Q is declared which is used to count the number of clock pulses received. The 8th and 11th line indicates the condition of each mode. When stw on = 0, the divider is in the normal
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mode. At every positive edge of the clock, Q increases by 1. When Q reaches 27000000, clkpulse will output 1, in which case the frequency is divided to 1 Hz. When stw on = 1, the divider is in the stopwatch mode. When Q reaches 270000, clkpulse will output 1, in which case the frequency is divided to 100 Hz.
Listing 2.1: Frequency divider module clk_gen ( clock , clkpulse , stw_on ); input clock , stw_on ; output reg clkpulse ; integer Q;
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always@ ( posedge clock ) begin i f (~ stw_on )
// normal begin i f (Q <=27000000) begin Q = Q +1; clkpulse =0; end else begin Q =0; clkpulse =1; end end else // stopwatch begin i f (Q <=270000) begin Q = Q +1; clkpulse =0; end else begin Q = Q +1; clkpulse =0;
Q =0; clkpulse =1; end end end endmodule
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2.1.2
counter unit & counter ten
As the clock is sexagesimal, the maximum numbers of units and tens are different. Therefore, two kinds of counters were designed. As indicated by the names, the counter unit is for the unit place and the counter ten is for the tens place. In the clock mode and alarm mode, counter unit counts from 0 to 9 in every cycle, however, counter ten counts from 0 to 5. As the functions of both counters are same, only counter unit will be introduced as an example. counter ten will be listed in the appendics.
The counter module should be the most important module, as all the functions of the clock are realized by it. As shown in Listing 2.2, there are 9 inputs and 4 outputs in this module.
The valueout output the number which indicates the time. The clk receives the 1 Hz or
100 Hz clock signals generated by the frequency divider. The clear, set and add are used when the user needs to clear or set the time. The rest ports can be allocated to the three functions. The ports with prefix ”cl ” are for clock mode. The ports with prefix ”stw ” are for stopwatch mode. The ports with prefix ”alarm ” are for alarm mode. In some conditions, different modes are expected to work simultaneously, which is often called the background processing. For example, when the stopwatch mode is being used, though the clock mode is not displayed, it should be also running in the background. Therefore, this allocation aims to avoid interruption between different modes when they are working at the same time. The following paragraphs will introduce each mode individually.
Clock mode As defined in the 16th line, the condition of clock mode is when both alarm and stopwatch are off. The algorithm of the clock mode part can be indicated by the following flowchart in Fig 2.1. When both clear and set switch are off, the clock is in normal mode.
The value indicating the time increases from 0 to 9 and then assign back to 0. When the value equals to 9, the cl rco will be assigned to 1 to indicate one cycle has been completed.
As shown in the 35th line, when the clear is on and set switch is off, the clock will be cleared, in which case the value is assigned to 0. As shown in the 41st line, when the set switch is on and the clear switch is off, the clock will be set, in which case value can be assigned to any value from 0 to 9.
Stop watch mode As shown in the 93rd line, the stopwatch mode is in the condition when the stw on is switched on and the alarm on is switched off. As shown in 110th line, the stopwatch will start when stw en is on. There is not set function in the stopwatch mode. Furthermore, as mentioned previously, the clock mode is expected to run in the background in the stopwatch mode. As in the stopwatch mode the clock signals received from the frequency divider becomes 100 Hz, a variable Q is used to divide the frequency. At every positive edge of the clk signals, Q increases by 1. When Q reaches 100, it will be set to 0 again, in which case the frequency of Q is 1 Hz. Every time Q equals to 0, the clock in the background is processed one time. Except the background function and set function, the counter works in the same way as the clock mode.
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Figure 2.1: flowchart of counter unit
Alarm mode There are two parts in the codes that are responsible for the alarm mode.
One part is from 60th line to 90th line and the other one is from 30th line to 33th line.
The part from the 60th line is for alarm setting, which is on when alarm on is switched on and stw on is switched off. In this part, the alarm value is displayed. Similar to the stopwatch mode, the clock is also running in the background. When set is on, users can set the alarm value to any value from 0 to 9, just similar to the set function in the clock mode.
In the part from 30th to 33th line, the alarm value is not displayed, but it is held in the register. If the alarm en is on, the alarm rco will be assigned to 1, which indicates that the alarm is ringing, once the cl value equals to the alarm value. The flowchart which indicates the algorithm of alarm mode is shown below.
i f ((~ stw_on ) & (~ alarm_on )) begin i f ( cl_en & (~ clear ) & (~ set )) begin i f ( cl_value !=4 ’ b1001 ) cl_value = cl_value +1; e l s e i f ( cl_value ==4 ’ b1001 ) cl_value =4 ’ b0000 ; i f ( cl_value ==4 ’ b1001 ) cl_rco =1; else cl_rco =0; end // normal
// Alarm
i f (( cl_value == alarm_value ) & alarm_en ) alarm_rco =1; else alarm_rco =0;
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// clear
i f (( clear )&(~ set )&(~ alarm_on )&(~ stw_on )) begin cl_value =4 ’ b0000 ; cl_rco =0; end 35
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// set
i f (( set )&(~ clear )&(~ alarm_on )&(~ stw_on )) begin i f (~ add ) begin i f ( cl_value !=4 ’ b1001 ) cl_value = cl_value +1; e l s e i f ( cl_value ==4 ’ b1001 ) cl_value =4 ’ b0000 ; end else cl_value = cl_value ; i f ( cl_value ==4 ’ b1001 ) cl_rco =1; else cl_rco =0; end valueout = cl_value ; end //−−−−−−−−−−−−−−−−−−Alarm−mode−−−−−−−−−−−−−−−−−−−−−−−−−−−−
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e l s e i f ( alarm_on & (~ stw_on )) begin // the clock also runs in the background
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i f ( cl_en ) begin i f ( cl_value !=4 ’ b1001 ) cl_value = value +1; e l s e i f ( cl_value ==4 ’ b1001 ) cl_value =4 ’ b0000 ; i f ( cl_value ==4 ’ b1001 ) cl_rco =1; e l s e cl_rco =0; end // alarm
i f (( set ))
// set begin i f (~ add ) begin i f ( alarm_value !=4 ’ b1001 ) alarm_value = value +1; e l s e i f ( alrm_value ==4 ’ b1001 ) alarm_value =4 ’ b0000 ; end else alarm_value = alarm_value ; end valueout = alarm_value ; end //−−−−−−−−−−−−−−−−−−stopwatch−mode−−−−−−−−−−−−−−−−−−−−−−−−
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e l s e i f ( stw_on & (~ alarm_on )) begin Q = Q +1; i f ( Q ==100)
Q =0;
// divide frequency
// the clock also runs in the background
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i f (( Q ==0) & cl_en ) begin i f ( cl_value !=4 ’ b1001 ) cl_value = value +1; e l s e i f ( cl_value ==4 ’ b1001 ) cl_value =4 ’ b0000 ; i f ( cl_value ==4 ’ b1001 )
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cl_rco =1; e l s e cl_rco =0; end // stopwatch
i f ( stw_en ) begin i f ( stw_value !=4 ’ b1001 ) stw_value = stw_value +1; e l s e i f ( stw_value ==4 ’ b1001 ) stw_value =4 ’ b0000 ; i f ( stw_value ==4 ’ b1001 ) stw_rco =1; e l s e stw_rco =0; end i f ( clear ) begin stw_value =4 ’ b0000 ; stw_rco =0; end valueout = stw_value ; end 110
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endmodule
2.1.3
display
The display module can be also called binary code decoder. It is designed to convert the binary code received from the counter to the code that can be used by the 7-segment displayer. As shown in the figure below, the 7 leds in the displayer are numbered from 0 to 6.
The led will light when it is connected to low voltage level. For example, as shown in the
10th line, when bcd sends a value 0011 in binary code, which indicates 3 in decimal code, display will convert it to 0000110. In this case, the leds numbered by 0, 1, 2, 3, 6 will light and indicate a ”3”.
After the codes were designed, three blocks were created as shown in the following subsections. inputs and outputs were connected to each block for the vector waveform analysis.
2.2.1
frequency divider
Figure 2.4: frequency divider
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2.2.2
counter
Figure 2.5: frequency divider
2.2.3
display
Figure 2.6: frequency divider
2.3
Vector waveform simulation
Through vector waveform simulation, the blocks were analyzed to check whether they could work as expectation. In the following subsections, the waveform of each blocks will be shown.
2.3.1
frequency divider
The figure below shows the waveform of frequency divider. A clock waveform with period of
10ns was given to the clock port. The stw on which is used to switch between normal mode and stopwatch mode was set to 0 in the first simulation and was set to 1 in the second one.
Figure 2.7: frequency divider in normal mode
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Figure 2.8: frequency divider in stopwatch mode
Comparing Fig. 2.7 and Fig. 2.8, it can be found that in the second simulation, in which the frequency divider is switched to the stopwatch mode, the frequency of the output clk pulse is much higher. The frequency of the output in the stopwatch mode is 100 times of the one in the normal mode. This phenomenon matches the codes and the design purpose.
2.3.2
counter unit & counter tens
As the blocks counter unit and counter tens have the same functions and working principle, only counter unit was analyzed. The simulation of counter includes three parts, which are normal mode, stopwatch mode and alarm mode.
Normal mode Both alarm on and stw on were set to 0 in the normal mode. In the simulation of normal mode, the clear and set functions were analyzed. As shown in the figure below, Port 0 to 7 are inputs and the others are the outputs. At first, with no switch changed, the valueout kept counting from 0 to 3, until there occurred a pulse of clear after
2.56 µs. The valueout was then set to 0 and continued to count from 0. From about 5.12 µs to 13 µs, the switch set was on, in which case, the counter stop counting until the voltage level of add was set to low. At about 13 µs, with the set switched off, the counter start to count in the normal mode again. As shown in the Fig. 2.9, there was a pulse of cl rco between 15 µs to 17 µs, which indicated that the counter had just completed one cycle from
0 to 9.
Figure 2.9: Counter in normal mode
stopwatch mode When stw on is on and alarm on is off, the counter is in the stopwatch mode. In the stopwatch mode, the counter counts only if both stw on and stw en is on.
Therefore, as shown in Fig. 2.10, in the periods from 0 to about 3 µs and from 7.68 µs to
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about 13 µs, the valueout kept constant, though stw on is on. In the interval between 7.68 µs and 10.24 µs, a pulse of clear was given to check the clear function in stopwatch mode.
As shown, at the first positive edge of the clock signal in the period clear is on, valueout was set to 0, which matches the expectation.
Figure 2.10: Counter in stopwatch mode
Alarm mode When stw on is off and alarm on is on, the counter is in the alarm mode.
As shown in Fig. 2.11, before alarm on was switched on after 2.56 µs, the counter was in normal mode. After alarm on was switched on, valueout displayed the value of alarm. As shown in the interval between about 7 µs and 12µs, the counter will count only if both set and add are on, in which case the value of alarm can be set to any value between 0 to 9. It can be found at the negative edge of the set pulse, the value of alarm was set to 5, which indicates that the counter should alarm every time it counts to 5. To check this function, the switch alarm on was switched off to switch the counter to normal mode and alarm en was switched on at 12.8 µs to enable the counter to alarm. As shown at about 14 µs and
24 µs, there were 2 alarm rco pulse which indicated that the counter was alarming. These phenomenons matches the expectation.
Figure 2.11: Counter in alarm mode
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2.3.3
display
To check the display block, the input was initially set to values 0 to 9 in binary. The resultant waveforms are shown in the Fig. 2.12. As mentioned previously, take ’3’ as an example, when the input bcd is 3, the leds 1, 2, 3, 4 and 7 should be low to light. The results shown in the figure matches the expectation.
Figure 2.12: Display
2.4
Block diagram
The Fig. 2.13 shows the whole block diagram. As shown, one frequency divider, four counters and four displays were used. Among the four counters, if counting from the bottom one, the first and third counters are counter unit and the other two are counter tens. The first counter is for the unit of second. The second counter is for the tens of second. The third counter is for the unit of minute. The forth counter is for the tens of the minute.
As the block diagram is too large to be shown clearly in this report, the following two figures in this section show parts of the block diagram. Some important points about the diagram will be also mentioned.
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Figure 2.13: Display
As shown in Fig. 2.15, there are some inputs that are connected to all the counters, which includes clkpulse, stw on, alarm en, alarm on, clear and set.
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Figure 2.14: Display
The hierarchy is important for the counters to carry over. If counting from the bottom counter, the counters can be labeled as ’counter1’, ’counter2’, ’counter3’ and ’counter4’. The hierarchy of the counters or the rules that the counters should follow to carry over are shown below. • counter2 cl en = counter1 cl rco
• counter2 stw en = counter1 stw rco
• counter3 cl en = counter2 cl rco && counter1 cl rco
• counter3 stw en = counter2 stw rco && counter1 stw rco
• counter4 cl en = counter3 cl rco && counter2 cl rco && counter1 cl rco
• counter4 stw en = counter3 stw rco && counter2 stw rco && counter1 stwc rco
Based on the hierarchy, the cl en, cl rco, stw en and stw rco ports were connected as shown in the figure below.
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Figure 2.15: Display
The alarm rco ports of the 4 counters are connected to an AND gate and then connected to outputs. In this case, the outputs will be HIGH only if all the alarm rcos are on, which realize the alarm function.
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Chapter 3
Simulation Result
This chapter shows the waveforms when the whole block diagram was analyzed. Fig. 3.1 shows the normal mode of the clock. From the figure, the clock just kept counting in the normal mode.
Figure 3.1: Normal mode waveform
As shown in Fig. 3.2, the set and clear function of the normal mode was checked. At 1.28 µs, with the switch clear set to 1, the bcds were set to 0. During the interval from about 3 µs to 8 µs, with set on, the bcds only count when their corresponding cl add button was set to 0. From the figure, it can be found, the buttons from cl add0 to cl add3 were set to 0 for a certain period sequentially. As the phenomenon, the value of the bcds also increased by
1 in the same sequence. After set switched off, the clock turned back to normal mode and continued to count.
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Figure 3.2: Normal mode waveform
In the analysis in Fig. 3.3, the stopwatch mode was checked. It can be seen that the clock began to count when both stw on and stw en were on and the frequency was much higher in the normal mode. At 1.28 µs, with clear set to 1, the value of bcds were set to 0.
Figure 3.3: Normal mode waveform
The analysis of the alarm mode was shown in the Fig. 3.4. It can be found that the bcds displayed the value normal mode at first, but was switched to alarm mode at 1.28 µs with alarm on on. During the interval from about 2.56 µs to 6.4 µs, with both alarm on and set on, the value of bcds were able to change to any value by using the cl add buttons. The value of alarm mode was set to 00:25 finally. Then, alarm on was set off to switch back to normal mode and alarm en was set on to enable the counter to alarm. It can be seen that at 12.8 µs when the value of bcds was 00:25 , alarm led was on which indicates the counter was alarming.
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Figure 3.4: Normal mode waveform
From the above phenomenons, it is indicated that the counter worked well.
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Chapter 4
Conclusion
During this lab, students were required to design a digital clock on DE1 board. This report has first given an introduction of DE1 package and then described the methodology including codes and block diagrams. The simulation results part shows how the clock works. Through this lab, students have reviewed the knowledge of Verilog HDL and practiced the skills of programming.The knowledge and skills got in this lab will be significance in the future study in the field of Verilog HDL and microprocessor.
i f ((~ stw_on ) & (~ alarm_on )) begin i f ( cl_en & (~ clear ) & (~ set )) begin i f ( value !=4 ’ b0101 ) cl_value = cl_value +1; e l s e i f ( cl_value ==4 ’ b0101 ) cl_value =4 ’ b0000 ; i f ( cl_value ==4 ’ b0101 ) cl_rco =1; else cl_rco =0; end // normal
// Alarm
i f (( cl_value == alarm_value ) & alarm_en ) alarm_rco =1; else alarm_rco =0;
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// clear
i f (( clear ) & (~ set ) & (~ alarm_on ) & (~ stw_on )) begin value =4 ’ b0000 ; cl_rco =0; end 35
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// set
i f (( set ) & (~ clear ) & (~ alarm_on ) & (~ stw_on )) begin i f (~ add )
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begin i f ( cl_value !=4 ’ b0101 ) cl_value = cl_value +1; e l s e i f ( cl_value ==4 ’ b0101 ) cl_value =4 ’ b0000 ; end else cl_value = cl_value ; i f ( cl_value ==4 ’ b0101 ) cl_rco =1; else cl_rco =0; end valueout = cl_value ; end //−−−−−−−−−−−−−−−−−−timer−mode−−−−−−−−−−−−−−−−−−−−−−−−−−−−
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e l s e i f ( alarm_on & (~ stw_on )) begin // the clock also runs in the background
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i f ( cl_en ) begin i f ( cl_value !=4 ’ b0101 ) cl_value = cl_value +1; e l s e i f ( cl_value ==4 ’ b0101 ) cl_value =4 ’ b0000 ; i f ( cl_value ==4 ’ b0101 ) cl_rco =1; e l s e cl_rco =0; end // alarm
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i f (( cl_set ))
// set begin i f (~ add ) begin i f ( alarm_value !=4 ’ b0101 ) alarm_value = alarm_value +1; e l s e i f ( alarm_value ==4 ’ b0101 ) alarm_value =4 ’ b0000 ; end else alarm_value = alarm_value ; end valueout = alarm_value ;
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e l s e i f ( stw_on & (~ alarm_on )) begin Q = Q +1; i f ( Q ==100)
Q =0;
// the clock also runs in the background
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i f (( Q ==0) & cl_en ) begin i f ( value !=4 ’ b0101 ) cl_value = cl_value +1; e l s e i f ( cl_value ==4 ’ b0101 ) cl_value =4 ’ b0000 ; i f ( cl_value ==4 ’ b0101 ) cl_rco =1; e l s e cl_rco =0; end // stopwatch
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i f ( stw_en ) begin i f ( stw_value !=4 ’ b1001 ) stw_value = stw_value +1; e l s e i f ( stw_value ==4 ’ b1001 ) stw_value =4 ’ b0000 ; i f ( stw_value ==4 ’ b1001 ) stw_rco =1; e l s e stw_rco =0; end i f ( clear ) begin stw_value =4 ’ b0000 ; stw_rco =0; end valueout = stw_value ; end endmodule
