Free Essay

Error Codes

In: Computers and Technology

Submitted By markkevin
Words 1906
Pages 8
Synchronous dynamic random access memory (SDRAM)
- is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. The clock is used to drive an internal finite state machine that pipelines incoming commands. The data storage area is divided into several banks, allowing the chip to work on several memory access commands at a time, interleaved among the separate banks. This allows higher data access rates than an asynchronous DRAM.

Single in-line memory module random access memory(SIMMRAM)
- is a module containing one or several random access memory (RAM) chips on a small circuit board with pins that connect to the computer motherboard.

Dynamic random-access memory (DRAM)
- is a type of random-access memory that stores each bit of data in a separate capacitorwithin an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. Since even "nonconducting" transistors always leak a small amount, the capacitors will slowly discharge, and the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory.
Non-volatile random-access memory (NVRAM)
- is random-access memory that retains its information when power is turned off (non-volatile). This is in contrast to dynamic random-access memory (DRAM) and static random-access memory (SRAM), which both maintain data only for as long as power is applied.

Extended data-out dynamic random access memory(EDORAM)
-allows the data outputs to be kept active after the CAS\ signal goes inactive, using an additional signal OE\ to control the data outputs. This can be used in pipelined systems for overlapping accesses where the next cycle is started before the data from the last cycle is removed from the bus.

Network interface controller (NIC)
-is a computer hardware component that connects a computer to a computer network.

Integrated development environment (IDE)
- is a software application that provides comprehensive facilities to computer programmers for software development. An IDE normally consists of a source code editor, build automation tools and a debugger. Most modern IDEs offer Intelligent code completion features.
Small Computer System Interface (SCSI)
-is a set of standards for physically connecting and transferring data between computers and peripheral devices. The SCSI standards define commands, protocols and electrical and optical interfaces. SCSI is most commonly used for hard disks and tape drives, but it can connect a wide range of other devices, including scanners and CD drives, although not all controllers can handle all devices. The SCSI standard defines command sets for specific peripheral device types; the presence of "unknown" as one of these types means that in theory it can be used as an interface to almost any device, but the standard is highly pragmatic and addressed toward commercial requirements. Power-on self-test (POST)
- is a process performed by firmware or software routines immediately after a computer or other digital electronic device is powered on.

Dual in-line memory module
- comprises a series of dynamic random-access memoryintegrated circuits. These modules are mounted on a printed circuit board and designed for use inpersonal computers, workstations and servers. DIMMs began to replace SIMMs (single in-line memory modules) as the predominant type of memory module as Intel P5-based Pentium processors began to gain market share.

Fast page mode or FPM memory
-is slightly faster than conventional DRAM. While standard DRAM requires that a row and column be sent for each access, FPM works by sending the row address just once for many accesses to memory in locations near each other, improving access time.
Rambus inline memory module(RIMM)
- is not an acronym and is a trademark of Rambus incorporated for the Direct Rambus or DRAM (RDRAM) modules. RIMM is computer memory that resembles DIMMs; however, it is 184-pin and is available with built-in ECC support and Non-ECC at speeds up to 800MHz. RIMM modules are commonly used on the IntelPentium 4 motherboards.

Significant use of SIMM RAM and DIMM RAM
- A dual in-line memory module(DIMM), comprises a series of random access memory integrated circuits.
These are used in the Computers as a radom access memory. These began to replace SIMMs as the predominant type of memory module as Intel's Pentium processors began to control the market. The main difference between SIMMs and DIMMs is that SIMMs have a 32-bit data path, while DIMMs have a 64-bit data path. Single in-line memory modules, SIMMs, have a pin count of 72 which have contacts on one side of the memory module only. DIMMs, dual in-line memory modules, have since replaced SIMMs and offer a double sided module. DIMM is the current standard used throughout the computer industry for DDR and SDRAM.

What are the successor of the old CPU sockets?
- LGA 775, also known as Socket T, is an Intel desktop CPU socket. LGA stands for land grid array. Unlike earlier common CPU sockets, such as its predecessor Socket 478, the LGA 775 has no socket holes; instead, it has 775 protruding pins which touch contact points on the underside of the processor (CPU).
- LGA 1156, also known as Socket H or H1, is an Intel desktop CPU socket. LGA stands for land grid array. Its incompatible successor is LGA 1155.
- LGA 1366, also known as Socket B,[2][3] is an Intel CPU socket. This socket supersedes Intel's LGA 775 (Socket T) in the high-end and performance desktop segments. It also replaces the server-oriented LGA 771 (Socket J) in the entry level and is superseded itself by LGA 2011. LGA stands for land grid array. This socket has 1,366 protruding pins which touch contact points on the underside of the processor (CPU)[4] and accesses up to three channels of DDR3 memory via the processor's internal memory controller.
- LGA 2011, also called Socket R, is a CPU socket by Intel. It replaces Intel's LGA 1366 (Socket B) and LGA 1567 in the performance and high-end desktop and server platforms. The socket has 2011 protruding pins which touch contact points on the underside of the processor.

System Error Code Processor

* I.11002
[I.11002] A processor mismatch has been detected between one or more processors in the system. * I.1100A
[I.1100A] A processor microcode update failed. * I.18005
[I.18005] A discrepancy has been detected in the number of cores reported by one or more processor packages within the system. * I.18007
[I.18007] A power segment mismatch has been detected for one or more processor packages. * I.18008
[I.18008] Currently, there is no additional information for this event. * I.18009
[I.18009] A core speed mismatch has been detected for one or more processor packages. * I.1800B
[I.1800B] A cache size mismatch has been detected for one or more processor packages. * I.1800C
[I.1800C] A cache type mismatch has been detected for one or more processor packages. * I.1800D
[I.1800D] A cache associativity mismatch has been detected for one or more processor packages. * I.1800E
[I.1800E] A processor model mismatch has been detected for one or more processor packages. * I.1800F
[I.1800F] A processor family mismatch has been detected for one or more processor packages. * I.18010
[I.18010] A processor stepping mismatch has been detected for one or more processor packages. * I.2018002
[I.2018002] The device found at Bus % Device % Function % could not be configured due to resource constraints. The Vendor ID for the device is % and the Device ID is %. * I.3818001
[I.3818001] The firmware image capsule signature for the currently booted flash bank is invalid. * I.3818002
[I.3818002] The firmware image capsule signature for the non-booted flash bank is invalid. * I.3818003
[I.3818003] The CRTM flash driver could not lock the secure flash region. * I.58015
[I.58015] Memory spare copy initiated. * I.580A4
[I.580A4] Memory population change detected. * I.580A5
[I.580A5] Mirror Fail-over complete. DIMM number % has failed over to to the mirrored copy. * I.580A6
[I.580A6] Memory spare copy has completed successfully. * S.1100B
[S.1100B] CATERR(IERR) has asserted on processor %. * S.1100C
[S.1100C] An uncorrectable error has been detected on processor %. * S.2011000
[S.2011000] An Uncorrected PCIe Error has Occurred at Bus % Device % Function %. The Vendor ID for the device is % and the Device ID is %. * S.2011001
[S.2011001] An Uncorrected PCIe Error has Occurred at Bus % Device % Function %. The Vendor ID for the device is % and the Device ID is %. * S.2018001
[S.2018001] An Uncorrected PCIe Error has Occurred at Bus % Device % Function %. The Vendor ID for the device is % and the Device ID is %. * S.3020007
[S.3020007] A firmware fault has been detected in the UEFI image. * S.3030007
[S.3030007] A firmware fault has been detected in the UEFI image. * S.3040007
[S.3040007] A firmware fault has been detected in the UEFI image. * S.3050007
[S.3050007] A firmware fault has been detected in the UEFI image. * S.3060007
[S.3060007] A firmware fault has been detected in the UEFI image. * S.3070007
[S.3070007] A firmware fault has been detected in the UEFI image. * S.3818004
[S.3818004] The CRTM flash driver could not successfully flash the staging area. A failure occurred. * S.3818007
[S.3818007] The firmware image capsules for both flash banks could not be verified. * S.51003
[S.51003] An uncorrectable memory error was detected in DIMM slot % on rank %. * S.51006
[S.51006] A memory mismatch has been detected. Please verify that the memory configuration is valid. * S.51009
[S.51009] No system memory has been detected. * S.5100A
[S.5100A] Memory is present within the system but could not be configured. Please verify that the memory configuration is valid. * S.58008
[S.58008] A DIMM has failed the POST memory test. * S.68005
[S.68005] An error has been detected by the the IIO core logic on Bus %. The Global Fatal Error Status register contains %. The Global Non-Fatal Error Status register contains %. Please check error logs for the presence of additional downstream device error data. * W.11004
[W.11004] A processor within the system has failed the BIST. * W.3818000
[W.3818000] TPM communication failure * W.3818005
[W.3818005] The CRTM flash driver could not successfully flash the staging area. The update was aborted * W.50001
[W.50001] A DIMM has been disabled due to an error detected during POST. * W.58001
[W.58001] The PFA Threshold limit (correctable error logging limit) has been exceeded on DIMM number % at address %. MC5 Status contains % and MC5 Misc contains %. * W.58007
[W.58007] Invalid memory configuration (Unsupported DIMM Population) detected. Please verify memory configuration is valid. * W.580A1
[W.580A1] Invalid memory configuration for Mirror Mode. Please correct memory configuration. * W.580A2
[W.580A2] Invalid memory configuration for Sparing Mode. Please correct memory configuration. * W.580A3
[W.580A3] Invalid memory configuration for Lock-Step Mode. Please correct memory configuration. * W.68002
[W.68002] A CMOS battery error has been detected

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