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Et1220 Unit 5 Lab Report

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Submitted By msamazzing
Words 591
Pages 3
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Part 1- Implement Asynchronous Counters
Theory:
1. What makes a counter asynchronous?
The counter is asynchronous because its clock is only applied to a single flip-flop.

2. What is the modulus or count range of the following counter?
16 cycles will count from 0-15

Planning: 3. What is the purpose of the ELVISmx Dig In instrument? display the output of the counter

Test Procedure: 4. Record the observed values from Lab 5 Table 5-1. Record the state number, the value of QDQCQBQA, the hexadecimal and decimal values. StateNumber | DataLine 7 | DataLine 6 | DataLine 5 | DataLine 4 | Hexadecimal | Decimal | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 2 | 0 | 0 | 1 | 0 | 2 | 2 | 3 | 0 | 0 | 1 | 1 | 3 | 3 | 4 | 0 | 1 | 0 | 0 | 4 | 4 | 5 | 0 | 1 | 0 | 1 | 5 | 5 | 6 | 0 | 1 | 1 | 0 | 6 | 6 | 7 | 0 | 1 | 1 | 1 | 7 | 7 | 8 | 1 | 0 | 0 | 0 | 8 | 8 | 9 | 1 | 0 | 0 | 1 | 9 | 9 | 10 | 1 | 0 | 1 | 0 | A | 10 | 11 | 1 | 0 | 1 | 1 | B | 11 | 12 | 1 | 1 | 0 | 0 | C | 12 | 13 | 1 | 1 | 0 | 1 | D | 13 | 14 | 1 | 1 | 1 | 0 | E | 14 | 15 | 1 | 1 | 1 | 1 | F | 15 | | | | | | | | | | | | | | |

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Part 2- Implement Synchronous Counters
Theory:
5. What makes a counter synchronous?
Because its clock is applied to each of the flip-flops.

6. What is the purpose of the ~U/D control signal for the 74191 Synchronous Counter? when low, counts up, when high, counts down

Test Procedure: 7. Provide the wiring diagram that converts this Mod16 counter into a Mod 10 counter. Us Microsoft Paint to draw the wire connections.

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Part 3- Semiconductor Memory
Theory:
8. Using Lab Figure 5-7, which memory cells are addressed if 1001 is applied to A0-A3? the read and write state of the memory

9. How many nibbles of data can be stored in the 74189 64-bit bipolar RAM IC?
16
10. Describe the purpose of the 74189 ~WE signal, what is the difference between ~WE and R/~W
. R/!W is also a control signal, it controls the read and write state of the memory.
WE when low enables the data on D0-D3 to be written to memory. When high enables the data in Q0-Q3 t be read from memory. Written memory

Planning: 11. Why are inverters required on the output of 74189 for the tested circuit? will complement the output of Q0 thru Q3

12. Why are 74189 data lines connected to the ELVISmx Dig Out instrument Data lines 0, 1 & 2 and ground? provide the data to be written into memory

Test Procedure: 13. Write the procedure to read memory from a memory location.
To read from the 74189 (0r 7489): The address must be changed to the desired memory location. The new address will immediately make the register value available on outputs QA-QD.

14. Write the procedure to write data to a memory location.
• The address must be changed to the desired memory location.
• The data to be stored must be applied on the 74189 (0r 7489) D0-D3 input lines.
• The WE signal must be toggled to low and then back to high. This latches the values on inputs D0-D3 into the register.

15. Record the observed values from Lab 5 Table 5-3. Record the memory values at the indicated address. Address | Data | 0010 | 5 | 0011 | 1 | 0110 | 7 | 0111 | 2 | 1010 | 4 | 1101 | 3 |

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