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Evolution of Microprocessor

In: Computers and Technology

Submitted By hermison07
Words 1044
Pages 5
Microprocessor Evolution:

4004 to Pentium-4

Joel Emer
Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology

Based on the material prepared by

Krste Asanovic and Arvind

November 2, 2005

First Microprocessor
Intel 4004, 1971

Image removed due to copyright restrictions. To view image, visit http://news.com.com/Images+Moores+L aw+turns+40/2009-1041_3-56490195.html

November 2, 2005

6.823 L15- 2
Emer

• 4-bit accumulator architecture
• 8µm pMOS
• 2,300 transistors
• 3 x 4 mm2
• 750kHz clock
• 8-16 cycles/inst.

6.823 L15- 3
Emer

Microprocessors in the Seventies

Initial target was embedded control
• First micro, 4-bit 4004 from Intel, designed for a

desktop printing calculator

Constrained by what could fit on single chip
• Single accumulator architectures

8-bit micros used in hobbyist personal computers
• Micral, Altair, TRS-80, Apple-II

Little impact on conventional computer market until VISICALC spreadsheet for Apple-II (6502,
1MHz)
• First “killer” business application for personal

computers

November 2, 2005

6.823 L15- 4
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DRAM in the Seventies

Dramatic progress in MOSFET memory technology 1970, Intel introduces first DRAM (1Kbit
1103)
1979, Fujitsu introduces 64Kbit DRAM

=> By mid-Seventies, obvious that PCs would soon have > 64KBytes physical memory November 2, 2005

Microprocessor Evolution

6.823 L15- 5

Emer

Rapid progress in size and speed through 70s
– Fueled by advances in MOSFET technology and expanding markets

Intel i432





Most ambitious seventies’ micro; started in 1975 - released 1981
32-bit capability-based object-oriented architecture
Instructions variable number of bits long
Severe performance, complexity, and usability problems

Motorola 68000 (1979, 8MHz, 68,000 transistors)
– Heavily microcoded (and nanocoded)
– 32-bit general purpose register architecture (24 address pins)
– 8 address registers, 8 data registers

Intel 8086 (1978, 8MHz, 29,000 transistors)
– “Stopgap” 16-bit processor, architected in 10 weeks
– Extended accumulator architecture, assembly-compatible with 8080
– 20-bit addressing through segmented addressing scheme
November 2, 2005

6.823 L15- 6
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Intel 8086
Class
Data:

Register
AX,BX
CX
DX

Purpose
“general” purpose string and loop ops only mult/div and I/O only

Address:

SP
BP
SI,DI

stack pointer base pointer (can also use BX) index registers

Segment:

CS
SS
DS
ES

code segment stack segment data segment extra segment

Control:

IP
FLAGS

instruction pointer (low 16 bit of PC)
C, Z, N, B, P, V and 3 control bits

• Typical format R allows cheaper system
• Estimated sales of 250,000
• 100,000,000s sold

Software
• Microsoft negotiates to provide OS for IBM. Later buys and

modifies QDOS from Seattle Computer Products.

Open System





Standard processor, Intel 8088
Standard interfaces
Standard OS, MS-DOS
IBM permits cloning and third-party software

November 2, 2005

6.823 L15- 7
Emer

The Eighties:
Personal Computer Revolution

6.823 L15- 8
Emer

Personal computer market emerges
– Huge business and consumer market for spreadsheets, word

processing and games

– Based on inexpensive 8-bit and 16-bit micros: Zilog Z80, Mostek

6502, Intel 8088/86, …

Minicomputers replaced by workstations

– Distributed network computing and high-performance graphics for scientific and engineering applications (Sun, Apollo, HP,…)
– Based on powerful 32-bit microprocessors with virtual memory,

caches, pipelined execution, hardware floating-point

– Commercial RISC processors developed for workstation market

Massively Parallel Processors (MPPs) appear
– Use many cheap micros to approach supercomputer performance
(Sequent, Intel, Parsytec)
November 2, 2005

The Nineties

6.823 L15- 9
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Advanced superscalar microprocessors appear

• first superscalar microprocessor is IBM POWER in 1990

MPPs have limited success in supercomputing market

• Highest-end mainframes and vector supercomputers survive
“killer micro” onslaught

64-bit addressing becomes essential at high-end
• In 2004, 4GB DRAM costs 2x size of P-III

• Clock frequency rising faster than transistor speed
– deeper pipelines, fewer logic gates per cycle
– more advanced circuit designs (each gate goes faster)

⇒ Takes multiple cycles for signal to cross chip

November 2, 2005

Visible Wire Delay in P-4 Design

6.823 L15- 31
Emer

1
TC Next IP
2
3
TC Fetch
4
5
Drive
6
Alloc
7
Rename
8
9
Queue
Schedule 1
10
Schedule 2
11
12
Schedule 3
13
Dispatch 1
Dispatch 2
14
15 Register File 1
16 Register File 2
17
Execute
Flags
18
19 Branch Check
20
Drive
November 2, 2005

Pipeline stages dedicated to just driving signals across chip!

P-4 Microarchitecture

64 bits wide

Instruction TLB/
Prefetcher

Front-End BTB
(4K Entries)

6.823 L15- 32
Emer

System Bus

Instruction Decoder
Trace Cache (12K µops)

Trace Cache BTB
(512 Entries)

Microcode
ROM
µop Queue

Allocator/Register Renamer
Memory µop Queue
Memory Scheduler

Integer/Floating Point µop Queue
Fast

Slow/General FP Scheduler

Simple FP

Integer Register File/Bypass Network

AGU

2x ALU

2x ALU

Slow ALU

Load
Address

Store
Address

Simple
Instr.

Simple
Instr.

Complex
Instr.

FP
MMX
SSE
SSE2

Bus
Interface
Unit

FP Register/Bypass

AGU

Quad
Pumped
3.2 GB/s

FP
Move

L2 Cache
(256K byte
8-way)
48 GB/s

L1 Data Cache (8Kbyte 4-way)

November 2, 2005

Figure by MIT OCW.

256 bits

6.823 L15- 33
Emer

Microarchitecture Comparison

In-Order
Execution
Fetch
Decode

In-Order

Out-of-Order

Execution

Br. Pred.

In-Order

Resolve

Decode

Execute
Commit




Fetch

ROB
In-Order

Speculative fetch but not speculative execution branch resolves before later instructions complete

Completed values held in bypass network until commit •



Br. Pred.
Resolve

Execute

Out-of-Order

Commit
Speculative execution, with

branches resolved after later

instructions complete

Completed values held in rename registers in ROB or unified physical register file until commit

• Both styles of machine can use same branch predictors in front-end fetch pipeline, and both can execute multiple instructions per cycle
• Common to have 10-30 pipeline stages in either style of design
November 2, 2005

MIPS R10000 (1995)






6.823 L15- 34
Emer

0.35µm CMOS, 4 metal layers
Four instructions per cycle
Out-of-order execution
Register renaming
Speculative execution past 4 branches • On-chip 32KB/32KB split I/D
Image removed due to copyright cache, 2-way set-associative restrictions. • Off-chip L2 cache
To view the image, visit http://wwwvlsi.stanford.edu/group/chips_micropro_ • Non-blocking caches body.html Compare with simple 5-stage pipeline (R5K series)
• ~1.6x performance SPECint95
• ~5x CPU logic area
• ~10x design effort

November 2, 2005

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