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# Flip-Flops and Related Devices

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Flip-Flops and Related Devices
Multiple Choice

1 . A "D" flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states? [Hint] CLK = NGT, D = 0 CLK = PGT, D = 0 CLOCK NGT, D = 1 CLOCK PGT, D = 1 Both a and c

2 . Which statement BEST describes the operation of a negative-edge-triggered D flip-flop? [Hint] The logic level at the D input is transferred to Q on NGT of CLK. The Q output is ALWAYS identical to the CLK input if the D input is HIGH. The Q output is ALWAYS identical to the D input when CLK = PGT. The Q output is ALWAYS identical to the D input.

3 . The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the: [Hint] edge-detection circuit. NOR latch. NAND latch. pulse-steering circuit.

4 . As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be: [Hint] very long. very short. at a maximum value to enable the input control signals to stabilize. of no consequence as long as the levels are within the determinate range of value.

5 . Determine the output frequency for a frequency division circuit that contains twelve flip-flops with an input clock frequency of 20.48MHz. [Hint] 10.24 kHz 5kHz 30.24kHz 15kHz

6 . An active-HIGH input S-C latch has a 1 on the S input and a 0 on the C input. What state is the latch in? [Hint]

7 . What is one disadvantage of an S-C flip-flop? [Hint] It has no Enable input. It has an invalid state. It has no CLOCK input. It has only a single output.

8 . Which of the following is correct for a clocked D latch? [Hint] The output toggles if one of the inputs is held high. Q output follows the input D when the ENABLE is high. Only one of the inputs can be high at a time. The output complement follows the input when enabled.

9 . Edge-triggered flip-flops must have: [Hint] very fast response times. at least two inputs to handle rising and falling edges. a pulse transition detector. active-low inputs and complemented outputs.

10 . What is the significance of the J and K terminals on the J-K flip-flop? [Hint] There is no known significance in their designations. The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also high. The letters represent the initials of Johnson and King, the co-inventors of the J-K flip-flop. All of the other letters of the alphabet are already in use.

11 . If both inputs of an S-C flip-flop are low, what will happen when the clock goes high? [Hint] An invalid state will exist. No change will occur in the output. The output will toggle. The output will reset.

12 . Which of the following best describes the action of pulse-triggered FF's? [Hint] The clock and the S-C inputs must be pulse shaped. The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock. A pulse on the clock transfers data from input to output. The synchronous inputs must be pulsed.

13 . Which of the following is a disadvantage of the S-C master-slave flip-flop? [Hint] The outputs do not change when both inputs are low. There is no complementary output. Data can only be entered on the leading edge of the clock. An invalid output state exists if both inputs are high.

14 . Which of the following is not generally associated with flip-flops? [Hint] Hold time Propagation delay time Interval time Set-up time

15 . The waveforms shown in Figure 5-1 are applied to a gated D latch, which is initially RESET. Which of the areas identified on the Q waveform is incorrect?

[Hint] a b c d

16 . What is another name for a one-shot? [Hint] Monostable Multivibrator Bistable Astable

17 . Given the waveforms for the S-C flip-flop in Figure 5-2, what is wrong with the circuit? [Hint] The Q output should be high at the beginning of the second clock pulse. The IC is defective. When both C and S are high at the same time, the output is unpredictable. Nothing is wrong with the circuit. The outputs should change on the trailing edge of the clock; the clock signal is inverted. The outputs should have toggled on the leading edge of the second clock pulse; the IC is bad.

18 . A gated S-C latch and its associated waveforms are shown in Figure 5-3. What, if anything, is wrong and what could be causing the problem? [Hint] The output is always low; the circuit is defective. The Q output should be the complement of the output; the S and R terminals are reversed. The Q should be following the R input; the R input is defective. There is nothing wrong with the circuit.

19 . Determine which of the output waveforms is correct for the master-slave D flip-flop shown in Figure 5-4.

[Hint] Qa Qb Qc Qd

20 . The 7472 AND-gated master-slave J-K flip-flop is shown in Figure 5-5 with a timing diagram. Examine the output waveform and determine what might be wrong with the circuit. The Q output is initially LOW and the PRESET and CLEAR are high. Determine whether or not a problem exists, and if so, what could be causing the problem.

[Hint] The output is correct; no problem exists. The output is incorrect; J1 is a constant HIGH. The output is incorrect; K3 is a constant LOW. The output is incorrect; Q is shorted to Vcc.

21 . A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem? [Hint] The power supply is probably noisy. The switch contacts are bouncing. The socket contacts on the register IC are corroded. The register IC is intermittent and failure is imminent.

22 . The circuit in Figure 5-6 fails to function; the inputs are checked with a logic probe and the following indications are obtained: C, J1, J2, J3, K1, K2, and K3 are pulsing. Q and CLR are HIGH. Q and PRE are LOW. What could be causing the problem? [Hint] There is no problem. The CLOCK should be held HIGH. The PRE is stuck LOW. The CLR is stuck HIGH.

23 . A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected? [Hint] The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being used. The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of the terminals to correct the problem. A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a NAND gate. A race condition exists between the CLOCK and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K flip-flop.

24 . Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown in Figure 5-7. Determine if the circuit is functioning properly, and if not, what might be wrong. [Hint] The circuit is functioning properly. Q2 is incorrect; the flip-flop is probably bad. The input to flip-flop 3 (D2) is probably wrong; check the source of D2. A bad connection probably exists between FF-3 and FF-4, causing FF-3 not to reset.

25 . A 555 timer is connected for astable operation as shown in Figure 5-8 along with the output waveform. It is determined that the duty cycle should be 0.5. What steps need to be taken to correct the duty cycle, while maintaining the same output frequency?

[Hint] Increase the value of C. Increase Vcc and decrease RL. Decrease R1 and R2. Decrease R1 and increase R2.

26 . In VHDL, in which declaration section is a COMPONENT declared? [Hint] Architecture Library Entity Port map

27 . In VHDL, how many inputs will a primitive JK flip-flop have? [Hint] 2 3 4 5

28 . Which is not an Altera Primitive port identifier? [Hint] clk ena clr prn

29 . In VHDL, how is each instance of a component addressed? [Hint] A name followed by a colon and the name of the library primitive A name followed by a semi-colon and the component type A name followed by the library being used A name followed by the component library number

30 . Which is not a real advantage of HDL? [Hint] Using higher levels of abstraction Tailoring components to exactly fit the needs of the project The use of graphical tools Both 1 and 2

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