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Hard-Wired Control Design

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Computer Organization and Architecture
Course design report

Hare-wired Control Design

1. Objective

a. To master the knowledge of Computer Organization and Arthitecture courses. To clearly understanding the working principles and interconnect of various modules of the computer system especially the hard-wired controller by making a comprehensive use of the knowledge. b. To learn the basic procecures and methods of using ISP technology to design and debug. To be familiar with the designing, simulating,and debugging tools for integrated development of software. And to experience the advantages of ISP technology from the traditional ones. c. To cultive the capability of independent work on science, and to obtain the experience of project design and assembling as well as debugging.
2.Equipment
1. TEC-4 system for COA experiments. 2. A dual trace oscilloscope. 3. A logical test pen. 4. An ispLSI1032 chip. 5. IspExpert of Lattice Co. Ltd.
3.Principles and Requirements The experiment is to design a hard-wired controller with an ispLSI1032 chip for the TEC-4 platform. The controller should perform five console instructions: KRD,KWE,KLD,KRR, nine machine instructions: ADD,SUB,MUL,AND,STA,LDA,JMP, JC,STP and the interrupts.
Preparations:
Timng Signal Generator: MF signal is generated by a crystal oscillator (frequency 1MHz), while producing T1, T2, T3, T4, W1, W2, W3, W4 timing signal, relationship as shown below. Where W1, W2, W3, W4 for the hard-wired controller to the beat signal. Experimental platform offers optional experimental area device and download IspLSI1032 chip socket, you can download from a PC, programming. DB, DP, DZ: DP = 1, the computer work in a single shot, according to a QD to send a timing signal T1, T2, T3, T4; DB = 1, the computer is in single step mode, press the send a QD Group W1, W2, W3, W4 clock pulse, and if the implementation process encountered TJ command to stop the pulse beat of T4 in the current moment. SKIP signal: When SKIP = 1, the signal from the current beat skips W4. Conclusisons of microperation signals are made as follows:
|Control Signal |Signal Role |Conditions of the signal |
|C |Generating the carry signal in the addition or subtraction |T4 on the rising edge |
|ALU_BUS |Allowing the results to be sent to the data bus |1 |
|LDDR1 |DR1 A port receiving the data from register stack when M1=0 |T3 on the dropping edge |
| |DR1 receiving DBUS date of the data bus when M1=1 | |
|LDDR2 |DR2 receiving the data from register stack B when M2=0 |T3 on the rising edge |
| |DR2 receiving DBUS date of the data bus when M2=1 | |
|WRD |RF dual-port register stack control write operation |1 and T2 on the rising edge |
|RS_BUS# |B-port RF control whether to send data on the DBUS |0 |
|LDER |Data on the DBUS into the temporary register ER |1 and T4 on the rising edge |
|SW_BUS# |SW7-SW0 data will be sent to DBUS |0 |
|CEL# |Select left port RAM dual-port memory |0 |
|LRW |Allowing RAM to read ports from the left |1 and T3 on the rising edge |
| |Allowing RAM to write port from the left |0 and T3 on the rising edge |
|CER |RAM and read data into the right port on the instruction bus INS |1 |
| |Forbidding the right port operation |0 |
|LDAR1 |Data entering the DBUS address register AR1 |1 and T4 on the rising edge |
|AR1_INC |AR1 value plus 1 |1 and T4 on the rising edge |
|LDAR2 |AR2 data from the PC entering into the program counter when M3=0 |1 and T2 on the dropping edge |
| |Data from the DBUS entering into AR2 when M3=1 | |
|LDR4 |Data from the DBUS entering into the R4 when M4=1 |1 and T2 on the dropping edge |
| |enter the data from the IR0-IR3 when M4=0 | |
|PC_ADD |ALU2 completing PC and adding the IR low 4 PC D |1 |
|PC_INC |PC+1 |1 |
|LDPC |Program counter PC receiving the address from the DBUS |1 and T4 on the rising edge |
|LDIR |Instructions from the RAM entering into the instruction register IR |1 and T4 on the rising edge |
|S2,S1,S0 |Selecting the type of arithmetic unit ALU op |1 |

4. Procedures Design Scheme a. Draw the flow chart of the console commands and the machine instructions. b. Draw flow chart of the decoding and timing control signal distribution table according to micro-operation, and each signal expressed by logical expressions. c. Write ABEL language source code by a logical expression. d.Downloaded the program to the chip. e. Connect and debug. f. Test. Specific Design Scheme: a.List the necessary console instructions and machine instructions.

|Name Of Console |Functions of Instructions |Format of Instructions |
|Instrucitons | | |
| | |SWC |SWB |SWA |
|KRR |Way of reading registers |1 |0 |0 |
|KRD |Way of reading dual-port registers |0 |0 |1 |
|KWE |Way of writing dual—port registers |0 |1 |0 |
|KLD |Way of loading registers |0 |1 |1 |
|PR |Way of starting the program |0 |0 |0 |
|Name of Machine |Prefix |Functions of |Format of Instructions |
|Instructionsns机器指令名| |Instructions | |
|称 | | | |
| | | |
| |KRR1 |
|PR2 |ADD |SUB |MUL |AND |LDA |
|SWB |27 | |LDDR2 |36 | |
|SWA |28 | |LDER |45 | |
|IR7 |15 | |LDIR |30 | |
|IR6 |14 | |LDPC |31 | |
|IR5 |13 | |LDR4 |40 | |
|IR4 |12 | |LRW |39 | |
|MF |5 | |PC_INC |63 | |
|T1 |6 | |PC_ADD |32 | |
|W1 |7 | |RS_BUS |47 | |
|W2 |8 | |SW_BUS |46 | |
|W3 |9 | |WRD |48 | |
|W4 |10 | |SKIP |70 | |
|C |29 | |TJ |69 | |
|CLR |3 | |M1 |7 | |
|INTQ |75 | | | | |
|ALU_BUS |56 |Output |M2 |8 | |
| | |PULLUP | | | |
|AR1_INC |36 | |M3 |37 | |
|CEL |38 | |M4 |33 | |
|CER |32 | |S0 |55 | |
|LDAR1 |35 | |S1 |54 | |
| | | | | | |
| | | | | | |
| | | | | | |
|LDAR2 |34 | |S2 |53 | |
| | | |INTS |77 | |
| | | |INTC |76 | |

Testing and Checking: 1. Realization of the basic instructions:
|Address |Instruction |Language |
|00H |LDA R0,[R2] |01011000 |
|01H |LDA R1,[R3] |01011101 |
|02H |ADD R0,R1 |00000100 |
|03H |JC+5 |10010101 |
|04H |AND R2,R3 |00111110 |
|05H |SUB R3,R2 |00011011 |
|06H |STA R3,[R2] |01001011 |
|07H |MUL R0,R1 |00100100 |
|08H |STP |0110XXXX |
|09H |JMP[R1] |100001XX |

Intialize the memory and register:
|Register |Storing Content |
|R2 |60H |
|R3 |61H |

|Memory Unit |Storing Content |
|60H |24H |
|61H |83H |

Calculating result:
R0=15H,R1=83H,R2=60H,R3=01H
Memory:60H: 46H 61H: 83H 2. Realization of the interrupts: Main Program:
|Address |Instruction |Language |
|20H |INTS |1011XXXX |
|21H |LDA R0,[R2] |01011000 |
|22H |ADD R0,R0 |00000000 |
|23H |ADD R0,R0 |00000000 |
|24H |ADD R0,R0 |00000000 |
|25H |ADD R0,R0 |00000000 |
|26H |ADD R0,R0 |00000000 |
|27H |ADD R0,R0 |00000000 |
|28H |ADD R0,R0 |00000000 |
|29H |JMP [R1] |10000100 |

Service program of interrups:
|Address |Instruction |Language |
|0A0H |ADD R0,R0 |00000000 |
|0A1H |IRET |1010XXXX |

6.Discussion
a. Problems when designing the procedure:

I met with the C260001 error in my computer when I finished compiling and started to run the simulating. Whatever I did the procedure just refused to run. I tried and tried until I did the same thing to another computer, and it worked well. I still wonder what the problem is, but there’s still no answer and left a problem for me to solve one day.

In the design process, I had some question on the T time of various signals at the same beat. I found them different, for example, in the W1 beat of KWE2, CEL # = 0, LRW = 0; and on the rising edge of T3, data was written into the RAM, but SKIP signal is effective as well. I can’t account for why. Fortunately, after looking up many materials, I transipired that when the SKIP signal is active, the generator didn’t jump to the W4 beat until all of the current signal was transferred; when TJ signals are effective, the generator is still sending off all the signals of the current beat, and finally stopped at T4 of the current beat.
b. Problems in proceeding and debugging Problems took place in proceeding and debugging as well. First comes the problems of connect. Because of the ignorance of connect, I got various errors in the result until I reconnect some wires which had broken off. How important the details are! During the operation, the mistake pressing of #CLR also accounted for many mistakes. And I was too confident with my capability of mental arithmetic,which makes a lot of strange problems. I’ve changed several machines during the procedures. But the real reason was my own faults. The carelessness and impatience will be enemies to my study afterwards. I have to overcome and correct them in the nearly future. Mistakes in the program writing has caused several failures as well. But in the process of checking and correcting, I’ve deepened my understanding of this course, and got a better acquaintance of the key points in program designing.

7.Conclusions Despite of various problems, I’ve succeeded in this course design. Although what I’ve reached is quite limited, I’ve got the knowledge I expected and some more important illuminations. The course design brings me deeper understanding of this course, including the sectional funcitions of the Data Path, various results of the signals, and the reading and designing of the flow chart. Moreover, my ability of operating is greatly improved. From the very beginning, I was hurry-scurry with these various wires and jacks. But now I am well versed with them. The simple progess means much more. And the tight link between theories and practise makes me know the basic procecures and methods in the hardware designing and debugging of ISP technology much better. Now I’ve been familiar with the usage of the designing, simulating, debugging tools of the integrated software development, and have full experience of the advantages of the ISP technology from the traditional ones. What’s more, I’ve made a better acquaintance to myself. First, my capability of practice and problem solution is improved. I’m now paying more attention the the details, with more patience, and knowing the importance of targets and plans better. These will help me to overcome my shortcomings and step to the success more steadily. I herein express my thanks to my teachers and school. As for myself, I’ll make more effort, bringing the spirits and harvest of this course design into my study and life. [pic][pic][pic][pic][pic][pic][pic][pic]
-----------------------
LDIAR

RS1 RS0

RS-BUS#

M1

LDDR1(T3)

M2

LDDR2(T3)

S2

S1

ALU-BUS

T4

S0

C

Figure of data access

ALU2

ALU

IAR

R4
MUX4

DR1
MUX1

Data Port Instruction Port RAM

AR1

PC

IR

Hard-wired controller

§c6RðS

ER

B Port A Port RF

A

B

··
·

WRD(T2)

WR1 WR0

RD1 RD0

LDER(T4)

SW-BUS#

Control Signal

C INTQ控制台

ER

B Port A Port RF

A

B

··
·

WRD(T2)

WR1 WR0

RD1 RD0

LDER(T4)

SW-BUS#

Control Signal

C INTQ

AR2
MUX3

IAR-BUS#

CEL#

LRW(T3)

CER

AR1-INC

DBUS

DBUS

INS

LDAR1(T4)

LDAR2(T2)

M3

LDPC(T4)

LDR4(T2)

M4

WR1 WR0
RD1 RD0
RS1 RS0

LDIR(T4)

DR2
MUX2

W4

W3

W2

W1

CER
LDIR
TJ

SW-BUS#
LDER

CER
LDIR
TJ

RS-BUS#
TJ

SW-BUS#
CEL#
LRW=0

SW-BUS#
CEL#
LRW=0

SW-BUS#
CEL#
LRW=0
SKIP

WRD
TJ

AR1-INC
TJ

SW-BUS#
M4=1
LDR4
LDPC
SSTO

SKIP

SKIP

SW-BUS#
LDAR1
M3=1
LDAR2
SSTO
TJ

SW-BUS#
LDAR1
SSTO
TJ

SW-BUS#
LDAR1
SSTO

SKIP

SW-BUS#
LDAR1
M3=1
LDAR2
SSTO
TJ

SKIP

ST

SKIP

Console instrucions flow chart

1100
KRR2

1011
KLD2

1010
KWE2

1001
KRD2

0000
PR1

0011
KLD1

0010
KWE1

AR1-INC

CEL#
LRW=1
TJ
SKIP

0100
KRR1

0001
KRD1

1000
PR2

1100
INTC

1011
INTS

1010
IRET

INTS

INTC

IAR_BUS#
M4=1
LDR4
LDPC

SKIP

SKIP

SKIP

INTQ=1

INTQ=0

SW-BUS#
M4=1
LDR4
LDPC

INTC
LDIAR
TJ

LDAR2

0000
PR1

Machine instrucion flow chart

W4

W3

W2

W1

0110
STP

1001 JC

1000
JMP

0100
STA

0101
LDA

0011
AND

0010
MUL

TJ

M4=01
LDR4
PC-ADD
LDPC

C

RS-BUS
M4=1
LDR4
LDPC

ALU=A
ALU-BUS
CEL#
LRW=0

M1=0
LDDR1
M2=0
LDDR2

WRD

WRD

WRD

WRD

WRD

CEL#
LRW=1
LDER

M1=0
LDDR1
M2=0
LDDR2

ALU=A&B
ALU-BUS
LDER

ALU=A*B
ALU-BUS
LDER

ALU=A-B
ALU-BUS
LDER

ALU=A+B
ALU-BUS
LDER

SKIP

SKIP

SKIP

M2=0
LDDR2
RS-BUS#
LDAR1
SKIP

RS-BUS#
LDAR1

M1=0
LDDR1
M2=0
LDDR2

M1=0
LDDR1
M2=0
LDDR2

IR

M3=0
LDAR2
CER
LDIR
PC-INC

C=0

C=1

0000
ADD

0001
SUB

1000
PR2

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