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Power in High Micro Processor

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Power in a high performance microprocessor

Submitted to: Submitted By:
Mr. Abhijit Bhattacharyya Shubham Gupta Roll No. 20 SECTION: K1111


I have taken efforts in this Term Paper. However, it would not have been possible without the kind support and help of many classmates and my teacher. I would like to extend my sincere thanks to all of them.
I am highly indebted to Mr. Abhijit Bhattacharyya for their guidance and constant supervision as well as for providing necessary information regarding the project & also for their support in completing the project.
My thanks and appreciations also go to my colleague in developing the project and people who have willingly helped me out with their abilities.

Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling. Designers are thus continuously challenged to come up with innovative ways to reduce power, while trying to meet all the other constraints imposed on the design. This paper presents an overview of the issues related to power consumption in the context of Intel CPUs. The main trends that are driving the increased focus on design for low power are described. System and benchmarking issues, and sources of power consumption in a high-performance CPU are briefly described. Techniques that have been tried on real designs in the past are described. The role of CAD tools and their limitations in this domain will also be discussed. In addition, areas that need increased research focus in the future are also pointed out
The drive towards increasing levels of performance has pushed frequencies higher and has increased the complexity of microprocessors. This has come at the cost of higher power consumption. The costs associated with packaging, cooling and power delivery have thus jumped to the forefront in the microprocessor industry. There is even concern that power consumption may set the limit to how much can be integrated on a chip, and how fast it can be clocked . The challenges for power reduction in high-performance generalpurpose CPUs are unique. First, the instruction-set and system architecture are designed for a wide market and for a wide range of applications. This restricts the search space for low-power solutions. Second, it is necessary that proposed solutions remain robust and scale gracefully across multiple technology generations. And finally, while significant power savings are desired, they must come at little or no performance impact. The aim of this paper is to highlight the key issues associated. Power, is associated with the power consumption while running an artificial piece of code specifically written to generate maximum CPU activity.

Figure 1 shows the power consumption for Intel CPUs. The X axis shows the technology generation and the Y-axis the maximum power consumption. As indicated by the dashed line in the main part of the curve, power consumption has been increasing for each new CPU generation. The points to the side of the main curve indicate newer versions of each processor family. These are implemented in newer semiconductor processes with smaller geometries than the lead processor in that family.

The reason is that increased power consumption directly impacts CPU and system cost. This cost has two components. The first is thermal cost, which is associated with keeping the devices below the specified operating temperature limits. Maintaining the integrity of packaging at higher temperatures also requires expensive solutions. The second component of the cost of power consumption is the cost of power delivery, i.e., the on-chip, on-package, and on-board decoupling capacitances and interconnect associated with the power distribution network. Increased power consumption at lower voltages increases the magnitude of the current drawn by the CPU. In addition, today’s design trends are such that the variability in the amount of current drawn from cycle to cycle is also increasing. These factors combine to make resistive and inductive noise a big problem. Dealing with this is becoming increasingly costly.
Figure 2 gives an idea of the range of dollar amounts associated with the above costs for different system components. As can be seen, when the CPU power is in the 35-40W range, the cost of each additional Watt goes above $1/W per chip. An interesting observation is that the power cost of the other system components (DRAM, chipsets, graphics) is on a steeper curve than the CPU. This is because the spatial layout of today’s system chassis designs is such that these components are harder to cool. This is likely to change with new designs, further increasing the relative importance of the CPU power cost.

CPU activity is a new design attribute that is needed for power estimation as well as for the choice of power savings techniques.
They have to come from traces of real applications. But power dissipation inside a CPU is a complex scenario. Figure 3 shows the need for defining multiple power specifications in this regard, using illustrative power traces. The first trace, labeled Max
Where Does the Power Go
Figure 4 shows the power breakdown for a recent highperformance
CPU, as obtained by detailed switch-level power simulation. As can be seen, the clock is the largest power consuming component. This includes the clock generator, the clock drivers, the clock distribution tree, the latches, and the clock loading due to all the clocked elements. The clock loading is actually the largest component of clock power. As shown in
Figure 5, even a simple latch presents a certain amount of capacitive load to the clock network (gate capacitance of 4 clocked devices in this example). This capacitance switches on every clock tick, causing significant power consumption even when the data inputs have low activity factor (AF), or are even totally stable (AF = 0).


Voltage Scaling
Power is proportional to the square of the supply voltage (Vcc).
This makes Vcc reduction as the most effective way for reducing power, and the industry has thus steadily moved to lower Vcc.
This trend should and will continue. However, the drive for higher performance is outstripping the benefits of voltage scaling, as illustrated in Figure 6. The figure shows the power, feature size, voltage, frequency, and relative die size of some recent
CPUs. Starting from a 5V part, there was an initial decrease in power when moving to a smaller technology at 3.3V. However, the power came back to original levels when the frequency was increased. The Pentium® Pro with its aggressive microarchitecture, saw an additional increase in power, even at
3.3V and a smaller technology.

Another issue with voltage scaling is that to maintain performance, threshold voltage (Vt) also needs to be scaled. At low Vt, leakage power starts becoming a bigger factor.

Clock Gating

The clock is the largest contributor to the CPU power. Reducing the switched capacitance on the clocks will thus have the most impact on total power. A practical and effective way to do this is to partition the clock network and allow only those portions to toggle that are needed on each cycle. This is achieved through clock gating . It is implemented by qualifying the different clock partitions by special “enable” signals. It is well suited for CPUs since it can often be easily integrated into existing clock networks A regular clock buffer can be changed into a qualifying gate at low area and performance overhead.


Power savings from the redesign of cell libraries can come from two sources: device sizing and restructuring of the logic and physical layout of cell. Device sizing for optimizing switching energy vs. delay, ensures that the libraries are designed with power “in mind” Figure 10 shows a power vs. delay curve for two different standard cell libraries. The transistor sizes in
Library 1 have been optimized for minimum delay as a target. If one were to change the optimization criteria of transistor sizes to that of energy and delay, one would get a lower power library
(Library 2). For Library 2, the delay penalty is small but the power reduction is greater, since the original library was in the steep non-optimal part of the curve. It has been seen in practice, that this extra delay can often be absorbed during circuit design, especially for non-critical paths. One can, therefore, get the same performance with Library2 and still have overall lower power. System Power Management

The interaction of the CPU with the rest of the system also provides avenues for reducing average power. Often the CPU is waiting for inputs from peripherals and its power is being wasted.
To reduce this waste, CPUs are now provided with a hierarchy of power states. Each state defines a certain level of activity on the CPUs and a certain time penalty for it to get back into a fully active state. Memory and I/O devices often also have similar power states. It is the system power management mechanism that monitors the system activity and enforces the movement of the system components between different power states [4]. System power management has its roots in mobile systems.
However, EPA requirements under the Energy Star program motivated the migration of these techniques to desktop systems.
A recent development in this area is a cross-company initiative called ACPI (Advanced Configuration & Power Interface) [1].
The recognition of the need to eliminate wasted power ensures that system power management will continue to be an area of high interest and active development.

Software Based Power Reduction

Traditionally the focus on low power design has been purely hardware based. This tends to ignore the fact that it is the software that executes on a CPU that determines its power consumption. Here a detailed instruction-level power model of the Intel486DX2 was built. The impact of software on the CPU’s power and energy consumption, and software optimizations to reduce these were studied. An important conclusion from this work was that incomplex CPUs like the 486DX2, software energy and performance track each other, i.e., for a given task, a faster program implementation will also have lower energy. This is because the CPU power consumption is dominated by a large cost factor (clocks, caches, etc.) that for the most part, does not vary much from one cycle to the other. There are some issues when this work is extended to recent CPUs. First, multiple-issue and out-of-order execution mechanisms make it hard to model power on a “per instruction” basis, and more complex power models are required. Also, increased use of clock gating implies that there is greater variation in power onsumption from cycle to cycle. However, it is expected that the relationship between software energy and power that was observed before will continue to hold. It is important to realize that software directly impacts energy/power consumption, and thus it should be designed to be efficient with respect to these metrics. A classic example of inefficient software is “busy wait loops”. Consider an application such as a spreadsheet that requires frequent user input. During the times when the spreadsheet is recalculating values, high CPU activity is desired in order to complete the recalculation in a short time. In contrast, when the application is waiting for the user to type in values, the CPU should be inactive and in a low-power state. However, a busy wait loop will prevent this from happening, and will keep the CPU in a high-power state. The power wastage is significant. For example, a 166MHz Pentium® Processor with MMXTM technology draws over 7 Watts in normal operation but only 1 Watt when halted. The Intel Power Monitor (IPM) is a publicly available software analysis tool that monitors system activityto provide information about.


High-performance CPU design presents unique challenges for research in power related issues. Certain directions here need increased research and development focus in the future. The highest priority is to continue pushing the voltage scaling treadmill. However, the technological and design hurdles in the path of using sub-1V supply voltages in large, high-performance CPUs have to be removed. Circuit styles and methodologies suited for low voltage are also needed. Microarchitectures in today’s high-performance CPUs are aimed at exploiting ever-increasing amounts of instruction-level parallelism. Organizational choices and tradeoffs are not made with power in mind. This needs to change and power consumption has to become a primary consideration here, since higher levels of design have the greatest leverage on the overall power consumption. Investigation of the hardware-software interface in CPUs will yield additional avenues for power reduction. Lower voltages, higher power consumption, more devices, and more clock gating - all these imply that the inductive noise problem will get worse. Increased innovation in packaging and power supplies would be needed to make sure that power delivery does not become the limiting factor for highperformance CPUs.

References * ACPI home page. * Chandrakasan, R. Brodersen. Minimizing power consumption in digital CMOS circuits. Proceedings of the IEEE 83(4), April 1995.

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