...Chapter 10 Instruction Sets: Characteristics and Functions What is an instruction set? - The complete collection of instructions that are understood by a CPU - is the part of the computer architecture related to programming, including the native data types, instructions, registers,addressing modes, memory architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the set of opcodes (machine language), and the native commands implemented by a particular processor. - Machine Code - Binary - Usually represented by assembly codes Elements of an Instruction -Operation code (Op code) - Do this - Specifies the operation to be performed (e.g.. ADD, I/O). The operation is specified by a binary code, known as the operation code, or opcode. - Source Operand reference - To this - The operation may involve one or more source operands, that is, operands that are inputs for the operation. - Result Operand reference - Put the answer here - The operation may produce a result. - Next Instruction Reference - When you have done that, do this... - This tells the CPU where to fetch the next instruction after the execution of this instruction is complete. Where have all the Operands gone? - The next instruction to be fetched is located in main memory or, in the case of a virtual memory system, in either main memory or secondary memory (disk). In most cases, the next instruction to be fetched immediately follows...
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...Set of Instructions Author Author Affiliation Abstract Instructions are set of guidelines that helps to perform a process or procedure. Making an USB fan is an easy “Do It Yourself” project. Anybody with access to a computer USB port can run a small fan. This paper describes instructions to be followed in order to make a USB fan. Title of Paper Equipment required: 1. Small 5 Volt dc Motor. 2. An adhesive glue, 3. A (exhausted) round shaped marker pen, 4. An USB cable, 5. Cutting tool like scissors or knife, 6. Wire stripper, 7. Tape, 8. Plastic gear available from any small toy car. 9. A circular piece of plastic of diameter 3” Instructions: 1. Firstly cut the USB cable at one end (it should be the end with female jack), 2. Locate red and black cables. Leave the rest. 3. Stripe out the copper wires using cable stripper, 4. Connect the red and black cable to that of the motor, 5. Attach the gear to the shaft of the motor, 6. Now make 8 cut to the center of the circular plastic. It would take small triangular shapes. Twist the triangular shaped wings of the fan slightly inwards, 7. Attach the circular plastic to the gear using glue, 8. Put the motor with the plastic on top of the marker and stick with the glue, 9. Now fix the other part of the marker on top of the cd vertically. 10. Connect the male USB jack to the USB port of a computer. The fan should move perfectly. Figure 1: Completed...
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...Instruction Set Sl.No. Instruction 1 nop 2 stop 3 adi xx 4 subi xx 5 xri xx 6 ani xx 7 ori xx 8 cmi xx 9ret 16 17 add 18 sub 19 xor 20 and 21 or 22 cmp 23 movs 24 movd 25 movi xx 26 store 27 load 28 push 29 pop 30jmpd xx 37 38jmpr 45 for the Single-Bus Processor Architecture Action Op Code (Hex) No action 00 Exit the program 01 02 [AR] ← [AR] + xx 03 [AR] ← [AR] – xx 04 [AR] ← [AR] ⊕ xx 05 [AR] ← [AR] ∧ xx 06 [AR] ← [AR] ∨ xx [AR] – xx (Flags only) 07 [PC] ← [[SP]], [SP] ← [SP]+1 08 to 0F if = 1 10-1F (n:0-F) [AR] ← [AR] + [] 20-2F (n:0-F) [AR] ← [AR] – [] 30-3F(n:0-F) [AR] ← [AR] ⊕ [] 40-4F(n:0-F) [AR] ← [AR] ∧ [] 50-5F(n:0-F) [AR] ← [AR] ∨ [] [AR] – [] (Flags only) 60-6F(n:0-F) 70-7F(n:0-F) [OR] ← [], [AR] ← [] 80-8F(n:0-F) [] ← [AR] 90-9F(n:0-F) [] ← xx [[AR]] ← [] [] ← [[AR]] [SP] ← [SP]–1, [[SP]] ← [] [] ← [[SP]], [SP] ← [SP]+1 [PC] ← xx if = 1 [PC] ← [AR] if = 1 A0-AF(n:0-F) B0-BF(n:0-F) C0-CF(n:0-F) D0-DF(n:0-F) E0 to E7 E8 to EF 46[SP] ← [SP]–1, [[SP]]← [PC], cd xx F0 to F7 53 [PC] ← xx if = 1 54[SP] ← [SP]–1, [[SP]]← PC], cr F8 to FF 61 [PC] ← [AR] if = 1 Flags: Zero (Z), Carry (CY), Sign (S), Parity (P) = u/z/nz/c/nc/p/m/op ⇒ FL = 0/Z/Z’/CY/CY’/S/S’/1 if Parity odd = r1/r2/r3/r4/r5/r6/r7/r8/r9/r10/r11/PC/SP/AR/OR ALU Function Codes: 0000 0001 0010 0011 0100 0101 0110 1111 ADD SUB XOR AND OR CMP A1 Architecture based on a Single Internal Data Bus RD WR Address Bus LMR Memory Address Register (MR) Memory and Input/Output Ports SRG Data...
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...V Term Paper Course code :CSE 211 Course title: Computer Organisation and Architecture Submitted to: Ramanpreet Kaur Lamba Madam Submitted by: K. Nabachandra Singha Very-Long Instruction Word (VLIW) Computer Architecture ABSTRACT VLIW architectures are distinct from traditional RISC and CISC architectures implemented in current mass-market microprocessors. It is important to distinguish instruction-set architecture—the processor programming model—from implementation—the physical chip and its characteristics. VLIW microprocessors and superscalar implementations of traditional instruction sets share some characteristics—multiple execution units and the ability to execute multiple operations simultaneously. The techniques used to achieve high performance, however, are very different because the parallelism is explicit in VLIW instructions but must be discovered by hardware at run time by superscalar processors. VLIW implementations are simpler for very high performance. Just as RISC architectures permit simpler, cheaper high-performance implementations than do CISCs, VLIW architectures are simpler and cheaper than RISCs because of further hardware simplifications. VLIW architectures, however, require more compiler support. INTRODUCTION AND MOTIVATION Currently, in the mid 1990s, IC fabrication technology is advanced enough to allow unprecedented implementations of computer architectures...
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...COMPLETE 8086 INSTRUCTION SET Quick Reference: AAA AAD AAM AAS ADC ADD AND CALL CBW CLC CLD CLI CMC CMP CMPSB CMPSW CWD DAA DAS DEC DIV HLT IDIV IMUL IN INC INT INTO IRET JA JAE JB JBE JC JCXZ JE JG JGE JL JLE JMP JNA JNAE JNB JNBE JNC JNE JNG JNGE JNL JNLE JNO JNP JNS JNZ JO JP JPE JPO JS JZ LAHF LDS LEA LES LODSB LODSW LOOP LOOPE LOOPNE LOOPNZ LOOPZ MOV MOVSB MOVSW MUL NEG NOP NOT OR OUT POP POPA POPF PUSH PUSHA PUSHF RCL RCR REP REPE REPNE REPNZ REPZ RET RETF ROL ROR SAHF SAL SAR SBB SCASB SCASW SHL SHR STC STD STI STOSB STOSW SUB TEST XCHG XLATB XOR Operand Types: REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP. SREG: DS, ES, SS, and only as second operand: CS. Memory: [BX], [BX+SI+7], variable, etc… Immediate: 5, -24, 3Fh, 10001101b, etc... Notes: • When two operands are required for an instruction they are separated by comma. For example: REG, memory • When there are two operands, both operands must have the same size (except shift and rotate instructions). For example: AL, DL DX, AX m1 DB ? AL, m1 m2 DW ? AX, m2 • Some instructions allow several operand combinations. For example: memory, immediate REG, immediate memory, REG REG, SREG • Some examples contain...
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...Solution* for Chapter 1 Exercise* Solutions for Chapter 1 Exercises 1.1 5, CPU 1.2 1, abstraction 1.3 3, bit 1.4 8, computer family 1.5 19, memory 1.6 10, datapath 1.7 9, control 1.8 11, desktop (personal computer) 1.9 15, embedded system 1.10 22, server 1.11 18, LAN 1.12 27, WAN 1.13 23, supercomputer 1.14 14, DRAM 1.15 13, defect 1.16 6, chip 1.17 24, transistor 1.18 12, DVD 1.19 28, yield 1.20 2, assembler 1.21 20, operating system 1.22 7, compiler 1.23 25, VLSI 1.24 16, instruction 1.25 4, cache • 1.26 17, instruction set architecture Solutions for Chapter 1 Exercises 1.27 21, semiconductor 1.28 26, wafer 1.29 i 1.30 b 1.31 e 1.32 i 1.33 h 1.34 d 1.35 f 1.36 b 1.37 c 1.38 f 1.39 d 1.40 a 1.41 c 1.42 i 1.43 e 1.44 g 1.45 a 1.46 Magnetic disk: Time for 1/2 revolution =1/2 rev x 1/7200 minutes/rev X 60 seconds/ minutes 3 4.17 ms Time for 1/2 revolution = 1/2 rev x 1/10,000 minutes/rev X 60 seconds/ minutes = 3 ms Bytes on center circle = 1.35 MB/seconds X 1/1600 minutes/rev x 60 seconds/minutes = 50.6 KB Bytes on outside circle = 1.35 MB/seconds X 1/570 minutes/rev X 60 seconds/minutes = 142.1 KB 1.48 Total requests bandwidth = 30 requests/sec X 512 Kbit/request = 15,360 Kbit/sec < 100 Mbit/sec. Therefore, a 100 Mbit Ethernet link will be sufficient. Solution* for Chapter X Exarclsm 1.49 Possible solutions: Ethernet, IEEE 802.3, twisted pair cable, 10/100 Mbit Wireless Ethernet, IEEE 802.1 lb, no medium...
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...fixed architecture and are typically RISC and cost more than micro program because of the time required to design the circuits , but they are faster. Micro program control units are slower than hardwired but are easier and cheaper to implement as the instructions are stored in special control memory. The control unit controls all data going in, out and inside the CPU. The control unit decodes the data from ram and turns it into an instruction depending on what instruction set the control unit is programed or hardwired to have. Then if the instruction involves any logic or mathamatical caluculations it gets sent to the alu where it gets calculated and outpeted to the accumulator. The ALU The ALU is an acronym for arithmetic and logic unit, this is one of the most important parts of the CPU as it does all of the calculations. The ALU is a big array of different logic gates that are interconnected to preform basic logical and mathematical operation such as putting adding numbers or xoring two values. How the ALU is designed makes a big difference in terms of how powerful the processor will be as the more complicated...
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... CPU The first thing we will discuss is the function of the CPU (Central Processing Unit) and its components. There are three primary components that make up the CPU, these are the ALU or the arithmetic/logic unit, the control unit (CU) and memory. The two components that collectively make up the CPU are the ALU and CU. Let’s take a look at the diagram above and I will explain what it all means. The logic and arithmetic unit is where all the data is stored and calculations are performed. The control unit basically interprets and controls all executions and processes instructions that it is given by other input types. In a typical CPU there is a I/O (input-output) interface which handles the input and output of data when it passes through the CPU to other devices that handle input/output data. The CPU architecture is defined by the major features it has, this is also known as ISA or instruction set architecture. It is these basics that include the number and types of registers, methods and how it addresses memory and basic design. With the typical technology advances that occur today, there have been several CPU architectures over the last few decades but only a small handful that last a long time. It is the evolution and the way technology expands and with each expansion there are newer features added and old ones updated. Memory Memory today is typically categorized as DRAM (dynamic random access memory), RAM or SRAM (static random access memory). There are a few...
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...project has been retrieved from the course textbook and those sources listed within the documentation that is being provided as part of this assignment. I have not given other fellow student(s) access to my code, script, diagram, etc., in any form. Part 1. Project Definition Instruction set architecture (ISA) describes the processor in terms of what the assembly language programmer sees the instructions and registers. All computer programs are translated to machine code for execution by the CPU. Once a program has been loaded into the computer’s memory. The program may then be executed. Many modern processor designs are so called RISC (Reduced Instruction Set Computer) designs which use relatively small instruction sets, in contrast to so called CISC designs such as the VAX and machines based on the Intel 8086 and Motorola 68000 microprocessor families. Operating instructions also include instructions that move data between registers and manipulate stacks. Memory-access instructions are those that transfer data between registers and memory. The CPU carries out the instructions that it finds in the computer’s memory. In order to carry out the task, the CPU must first transfer the instruction from memory into one of its registers. . (Johnson, 2014) Part 2. Requirements Collection The address bus and directional bus, i.e. information can only travel along it in a single direction, from the CPU to memory and other devices. The MAR register is a 16-bit register like all the...
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...equal to the current multiplied by the resistance V=IR * In an electrical system, power is equal to the voltage multiplied by the current P=VI * USE OHM TRIANGLE TO CACULATE CURRENT, VOLTAGE, OR RESISTANCE. * The CPU is the brain of the computer, it is sometimes referred to as the processor. * Most CPU sockets and processors in use today are built around the architectures of the pin grid array (PGA) and land grid array (LGA) * ZIF refers to the amount of force needed to install a CPU into the motherboard socket or slot. * When the CPU is executing one step of the program the rest of the data is stored in a special memory call the cache. * Two major artitectures are related to instruction sets: Reduced instruction set computer and Complex instruction set...
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...Instruction Sets: Characteristics and Functions The essential elements of a computer instruction are the opcode, which specifies the operation to be performed; the source and destination operand references, which specify the input and output locations and for the operation; and a next instruction reference, which is usually implicit. (understood) Opcode specify operation in one of the following general categories: arithmetic and logic operations; movement of data between two registers, register and memory or two memory locations; I/O; and control. Operand references specify a register or memory location of operand data. The type of data may be addresses, numbers, characters and logical data. A common architectural feature in processor is the use of stack, which may or may not be visible to the programmer. Stacks are used to manage procedure calls and returns and may be provided as an alternative form of addressing memory. The basic stacks operation are PUSH, POP, and operations on the top one or two stack locations. Stacks typically are implemented to grow from higher addresses to lower addresses. The machine instructions set provides the functional requirements for the CPU: Implementing the CPU is a task that in large part involves implementing the machine instructions set. MACHINE INSTRUCTIONS CHARACTERISTICS The operation of the CPU is determined by the instructions it executes referred to as Machine Instructions or computer instructions The collection of different...
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...Video Summary 3 In the video it explained the purposes, functions, and characteristics of a central processing unit (CPU). The CPU is a piece of hardware that carries out instructions to the computer and is considered the brains of the computer. The CPU can find information that was saved, it can decode information, and it can move memory from one place to another. The most important characteristic of the CPU is the operating speed which is the time required to execute an instruction or set of instructions. Topics presented in clip • Fan o Sits on top or next to the heat sink and pushes out the heat. • Heat Sink o The hardware on top of the CPU that moves the heat towards the fan in the computer. • CPU o The part of a computer that performs logical and arithmetical operations on the data as specified in the instructions. Terms and Definitions • CPU o Brains of the computer that carries out an instruction or a set of instructions. • Decode o Converts a coded message into a intelligible language. • Operating speed o The time required to execute an instruction or set of instructions. • ALU o Arithmetic and logic unit. o • System Bus (frontside bus) o Main communication system between motherboard and processor. • Instruction sets o Gives sets of directions to the processor. • Clock o Timing device for proper processor operation. • Hardware o Tools, machinery, and other durable equipment. Summary of My Thoughts My thoughts about the presentation...
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...CSE 6421 Research Assignment Explain how each architecture handles instruction fetch. ALPHA 21264: The instruction fetch is the stage 0 in Alpha 21264 instruction pipeline. It can fetch four instructions each cycle. It includes a branch predictor, two Mux for decode and validity check, a line/set prediction and an instruction cache. The branch prediction and the line/set prediction are used to increase fetch efficiency. The line and set prediction, associated with each instruction block, guides the professor to find the next instruction to fetch. The instruction cache is 64-Kbytes and two-way. Compared with Alpha 21164(8-Kbytes and direct-mapped), the hit rates increase significantly. Itanium 2: The instructions are fetched by the front-end structures. The instruction pointer is chosen from next linear IP, branch prediction resteer pointers or branch misprediction and instruction exception steer pointers by the front end and then presents to the instruction cache and translation look-aside buffer. The processor then uses prevalidated tags to decide to deliver instructions to which caches. In prevalidated tags design, the cache tags store the virtual address and compare with the identifier entry to find match line. It is faster to find out the cache hit address. MIPS R10000: The R10000 processor fetches...
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...2142CMIS3106380 March 9, 2014 Table of Contents I. Introduction 3 II. Reduced Instruction Set Computing (RISC) 3 III. Pipelining 3 IV. Cache Memory 4 V. Virtual Memory 4 VI. Conclusion 5 VII. Works Cited 5 I. Introduction The purpose of this paper is to investigate the evolution of and current trends in improving system performance with respect to RISC, pipelining, cache memory, and virtual memory. II. Reduced Instruction Set Computing (RISC) Reduced Instruction Set Computing also known as RISC is a type of microprocessor architecture. It is a CPU design strategy. The purpose of RISC was for design simplification. It increases the number of executed instructions thus increasing the CPU performance. (Joy) The RISC design was first proposed and implemented in the 1960s and has been constantly evolving. Since the late 1980’s, RISC has been more than doubling its performance every year and half. The RISC industry, which includes IBM and Sun Microsystems, is ever expanding with the focus on the speed of executing instructions per second along with the evolution of the computer industry. (Joy) III. Pipelining One characteristic of RISC processors is pipelining. With pipelining, instructions are able to be executed in a shorter period of time. The first step in pipelining is to find the instructions, then read the registers, decode the instructions, execute the instruction, access the data memory operands, and then load the results into the register...
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...www.jntuworld.com Code No: RR321402 RR SET-1 B. Tech III Year II Semester Examinations, December/January -2011-12 MICROPROCESSORS (MECHANICAL ENGINEERING(MECHATRONICS)) Time: 3 hours Max. Marks: 80 Answer any five questions All questions carry equal marks --1.a) What are various addressing mode in 8085 microprocessor? Explain with suitable example. b) Explain following instructions in detail with the help of examples. i) RAR ii) CPI data iii) CALL addr (Label) iv) SPHL v) XRI data. [8+8] 2.a) b) Draw the structure of 8086 flag register and explain the function of the flags with examples. Explain the function of the following instructions of 8086. i) IN ii) LAHF iii) LDS iv) XLAT v) XCHG [8+8] Discuss various branch instruction of 8086 microprocessor, that are useful for relocation? Write an 8086 assembly Language program to convert a BCD Number to a Binary Number. [8+8] What is an interrupt? Explain different types of interrupts supported by 8086 What are the priority-rules that follow to resolve the problem when two interrupt occurs at the same time? [8+8] Explain string manipulation instructions of 8086 with suitable examples. Write an assembly program to find out whether a given byte is in the string or not. If it is in the string, find out the relative address of the byte from the starting location of the string. [8+8] Distinguish between programmed I/O and interrupt I/O in case of 8086 processor. Interface an 8 × 8 key board using two 8255 ports and write a program...
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