Superscalar

Superscalar processing is the ability to initiate multiple instructions during the same cycle which is also called instruction level parallelism. Such superscalar processors implements different stages like instruction fetch and prediction which uses a cache to reduce latency and instruction buffers are used to hold the fetched instructions. Also conditional branches are recognized and determine there outcome. In instruction decoding , renaming and dispatching storage elements are identified and renaming is done by using physical register file which can be greater than or equal to logical register file. In the next stage instructions are issued and parallel execution is done. This can be done by using single, multiple queue method and with the use of reservation stations. Various dynamic instruction scheduling methods are used like tomasulo's algorithm. After this handling of memory operations is performed which uses translation lookaside buffers to speed up this translation process. Memory hierarchy is multiported to serve simultaneous multiple memory requests and this must be non blocking. Also store address buffers are used not to violate hazard conditions. In the final Committed state effects of instructions are allowed to modify the logical process state. Several checkpoints are identified in history buffer or reorder buffers are used to recover precise state. To follow all these steps software plays an important role which can assist by creating binary so that various stages can be made efficient. But there are certain limits like it becomes complex with increase in simultaneous instructions issued, widening gap between processor and main memory. To overcome this more sophisticated data design, better cache prefetch method, more developed memory hierarchies, VLIW etc. can be implemented.