Free Essay

Xyz.Doc

In: Computers and Technology

Submitted By ruchikab
Words 542
Pages 3
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : shift_register.ngr
Top Level Output File Name : shift_register
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO

Design Statistics
# IOs : 8

Cell Usage :
# BELS : 4
# INV : 1
# LUT3 : 3
# FlipFlops/Latches : 3
# FDC : 3
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 7
# IBUF : 4
# OBUF : 3
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s15cs144-6

Number of Slices: 2 out of 192 1% Number of Slice Flip Flops: 3 out of 384 0% Number of 4 input LUTs: 4 out of 384 1% Number of IOs: 8 Number of bonded IOBs: 8 out of 86 9% Number of GCLKs: 1 out of 4 25%

---------------------------
Partition Resource Summary:
---------------------------

No Partitions were found in this design.

---------------------------

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 3 |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
reset_inv(reset_inv1_INV_0:O) | NONE(q_0) | 3 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

Minimum period: 3.675ns (Maximum Frequency: 272.109MHz) Minimum input arrival time before clock: 3.366ns Maximum output required time after clock: 7.085ns Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk' Clock period: 3.675ns (frequency: 272.109MHz) Total number of paths / destination ports: 4 / 3
-------------------------------------------------------------------------
Delay: 3.675ns (Levels of Logic = 1) Source: q_1 (FF) Destination: q_0 (FF) Source Clock: clk rising Destination Clock: clk rising

Data Path: q_1 to q_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDC:C->Q 3 1.085 1.332 q_1 (q_1) LUT3:I1->O 1 0.549 0.000 q_mux0001<2>1 (q_mux0001<2>) FDC:D 0.709 q_2 ---------------------------------------- Total 3.675ns (2.343ns logic, 1.332ns route) (63.8% logic, 36.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 5 / 3
-------------------------------------------------------------------------
Offset: 3.366ns (Levels of Logic = 2) Source: mode (PAD) Destination: q_0 (FF) Destination Clock: clk rising

Data Path: mode to q_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 3 0.776 1.332 mode_IBUF (mode_IBUF) LUT3:I0->O 1 0.549 0.000 q_mux0001<2>1 (q_mux0001<2>) FDC:D 0.709 q_2 ---------------------------------------- Total 3.366ns (2.034ns logic, 1.332ns route) (60.4% logic, 39.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset: 7.085ns (Levels of Logic = 1) Source: q_1 (FF) Destination: q<1> (PAD) Source Clock: clk rising

Data Path: q_1 to q<1> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDC:C->Q 3 1.085 1.332 q_1 (q_1) OBUF:I->O 4.668 q_1_OBUF (q<1>) ---------------------------------------- Total 7.085ns (5.753ns logic, 1.332ns route) (81.2% logic, 18.8% route)

=========================================================================
CPU : 2.41 / 2.66 s | Elapsed : 2.00 / 3.00 s -->

Total memory usage is 124332 kilobytes

Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Similar Documents